I want to know what care should be taken while developing a testbench for RTL verification & intended to be used for netlist simulations.?
I am currently avoiding driving on observing signals inside the design...please provide ur tips on this...
I want to know what care should be taken while developing a testbench for RTL verification & intended to be used for netlist simulations.?
I am currently avoiding driving on observing signals inside the design...please provide ur tips on this...
Usually, sequential signals tend to remain available (albeit with a different name) after synthesis as well, hence a good guideline is to restrict monitoring of internal signals to sequential ones than combinatorial ones.
Another useful guideline is to use `define for signal names (if you use Verilog) so that the defines can be changed externally - no tweaking of TB needed. BTW, this also applies to any assertions you add to your design. We have this guideline in our PSL/SVA books as well (with example).
Any "sign-off" quality simulator can be used for netlist simulation - VCS, NC, MTI etc. One should also explore formal equivalence checking for RTL to Gate level equivalence.