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question on netlist & rtl verification

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ravi123

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I want to know what care should be taken while developing a testbench for RTL verification & intended to be used for netlist simulations.?
I am currently avoiding driving on observing signals inside the design...please provide ur tips on this...
 

aji_vlsi

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ravi123 said:
I want to know what care should be taken while developing a testbench for RTL verification & intended to be used for netlist simulations.?
I am currently avoiding driving on observing signals inside the design...please provide ur tips on this...

Usually, sequential signals tend to remain available (albeit with a different name) after synthesis as well, hence a good guideline is to restrict monitoring of internal signals to sequential ones than combinatorial ones.

Another useful guideline is to use `define for signal names (if you use Verilog) so that the defines can be changed externally - no tweaking of TB needed. BTW, this also applies to any assertions you add to your design. We have this guideline in our PSL/SVA books as well (with example).

HTH
Ajeetha
www.noveldv.com
 

eeeraghu

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What kind of tools are used here to compare the rtl and netlist simulations? are these netlist suitable for rtl simulators, Model sim, Ncsim..etc?

Kindly Help

Thanks and regards
Raghu
 

aji_vlsi

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eeeraghu said:
What kind of tools are used here to compare the rtl and netlist simulations? are these netlist suitable for rtl simulators, Model sim, Ncsim..etc?

Kindly Help

Thanks and regards
Raghu

Any "sign-off" quality simulator can be used for netlist simulation - VCS, NC, MTI etc. One should also explore formal equivalence checking for RTL to Gate level equivalence.

HTH
Ajeetha
www.noveldv.com
 

spauls

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assertions are helpful in both gate level and RTL simulations.
 

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