Question on ESD discharge current path?

[abcyin]

Hi, all,

A question arises when I'm designing the ESD circuit. you know there are some modes when you're testing the ESD circuits, among which the ESD stress between VDD and VSS should be checked. what I'd like to know is how the discharge current flows when a negative impluse occures at the VDD point while the VSS is connected to the Ground?

As the VSS is the highest potential, I thought the discharge current should go through the ndiode and then pdiode, finally to the VDD, and there would no current flowing through the power clamp transistor. BUT from the simulation, I see significant current flowing through the power clamp towards VDD, is this right? and why? I just couldn't explain this phenomenon.

Thanks in advance,
abcyin

 

[erikl]

There are a lot of different ESD circuits. You should show yours.

Did you consider that all MOSFETs contain parasitic anti-parallel junction diodes between source and drain?

 

[dick_freebird]

Think of ESD in terms of the current loop, not the pin
voltage. There will always be a return. Deducing what
path it will take, is all on you as a designer. You must
know the (often unadvertised / modeled) breakdown
attributes for all devices touching the loop, because
they may change that loop, and this includes "devices"
that most circuit designers will prefer to ignore (well
diodes, substrate-well-drain BJTs, closely spaced
conductors (X,Y,Z) as spark gaps, conductors as fuses.

If you had a desire to be thorough you would create
supplemental models that have "live" and accurate
breakdown response modeled (likely a subcircuit) and
do any-any pin zap simulations. But this entails a lot
of probably-not-appreciated char, modeling and design
work.

This is how I have approached pin protection design over
the last decade or so, anyway. If you are given I/Os to
use that have advertised capability and constraints and
requirements, then maybe you just follow the rules. But
custom analog never gives you much of that.