question on decoupling/bypass capacitor placement

[backdrill]

Take this for example, I have 3 capacitors acting as decoupling capacitor between my device's VDD pin and 5V power supply.
C1 - 0.01uF
C2 - 1uF
C3 - 10uF

What is the impact of the placement of decoupling or bypass capacitors to the signal/power integrity?

Possible placement scenarios:

a.) VDD pin - C1 - C2 - C3 - 5V
b.) VDD pin - C3 - C2 - C1 - 5V
c.) VDD pin - C3 - C1 - C2 - 5V
d.) VDD pin - C2 - C1 - C3 - 5V
e.) VDD pin - C2 - C3 - C1 - 5V
f.) VDD pin - C1 - C3 - C2 - 5V

Is there a difference on the signal/power integrity if I play with the order of placement of the capacitors?

 

[etmabreu]

Put the smaller one near the device. Reasoning: at high frequencies, wavelengths get smaller. This means that even a small PCB track can get big enough to act as an antenna. So, regarding AC, you must couple the power rail to ground as effectively as you can. For high frequencies a capacitor may stop acting like it should due to parasitics. This limit is reached first for big capacitors. Small capacitors can go further on frequency and still behave like a capacitor, so these are the ones that should be closer to the device.

If you can, at least for C1, use a ceramic capacitor with C0G dielectric.

 

[cyberrat]

What ^^he^^ said.

 

[marce]

Use MLCC X7R you can get smaller package size for all those values. COG is not realy required for decoupling, X7Rwill sufice, use smallest packages available for each value at voltage chosen for best results.

 

[D.A.(Tony)Stewart]

You must consider ESR and ESL of each device. You can choose these from various materials , form factors and values.
Plastic film have lowest ESR and ESL but cost more.
SMD have lower ESL.

Also consider source ESR, track impedance (LCR) and load ESR to determine minimal noise at load.
Normally bulk suppression at source minimizes current loop area near source for reducing track current and losses to load. But if track or path loss of pulsed current is significant, you need large caps at both ends.

Then RF suppression near load is best , either underneath or closest to driver and/or load, depending on effects of slew rate limiting.

If part of closed loop SMPS, follow regulator guidelines for min and max ESR for stability of loop. eg .1 to 1 ohm for some., lower for others.

If ESL of part is not given, they often provide SRF from which LC is related and min. impedance.
If cap is rated by phase angle or leakage @ 50/60Hz, then it is not a low ESR cap but intended for bulk rectifier filtering at low frequencies ,so not recommended.

 

[marce]

We are discussing chip decoupling capacitors, not SMPS which requires different and more careful placement and device size. Foe power pin decoupling the smallest size case available is best and MLCC provide this, as at best without using power integrity software decoupling for devices can follow the uidlines set out in numerous (ie ALL) chip manufacturers data sheets. And size is the critical factor as limiting parasitic impedance is paramount, so 0402 MLCC X7R rule the roost here (though 0201s have the edge due to even smaller size). Plastic film are to large for effective decoupling, to much inductance due to package size. Also use closely coupled power planes as the added planar capacitance will be the first source of capacitance seen by the device pins during switching, the on chipcapacitance being the first source of charge to supply the switching current requirements.
Remember most decoupling cap schemes are not much use above a certain frequency anyway