mike_bihan
Full Member level 3
I was being confused by some simulation results on 2 stage OP-AMP used as unity gain buffer.
First stage of the op-amp was the typical high-gain diff-amp. (current mirror used as load). 2nd stage was source follower.
When I was simulating the buffer (open loop) with Phase margin, the PM was actually increasing with the increase of capacitive loading on the output node. And the unity gain frequence doesn't change with the change of output capacitive loading.
What I am sure of was that the doninant pole was located at the output of first stage. I really do not understand what is the reason for that?
It looks like there is a zero also going lower frequence when the capacitive loading increase. This zero compensate the phase to have better phase margin.
Can anyone explain it for me or provide some material on that?
First stage of the op-amp was the typical high-gain diff-amp. (current mirror used as load). 2nd stage was source follower.
When I was simulating the buffer (open loop) with Phase margin, the PM was actually increasing with the increase of capacitive loading on the output node. And the unity gain frequence doesn't change with the change of output capacitive loading.
What I am sure of was that the doninant pole was located at the output of first stage. I really do not understand what is the reason for that?
It looks like there is a zero also going lower frequence when the capacitive loading increase. This zero compensate the phase to have better phase margin.
Can anyone explain it for me or provide some material on that?