Question on 2 stage buffer design

[mike_bihan]

I was being confused by some simulation results on 2 stage OP-AMP used as unity gain buffer.

First stage of the op-amp was the typical high-gain diff-amp. (current mirror used as load). 2nd stage was source follower.

When I was simulating the buffer (open loop) with Phase margin, the PM was actually increasing with the increase of capacitive loading on the output node. And the unity gain frequence doesn't change with the change of output capacitive loading.

What I am sure of was that the doninant pole was located at the output of first stage. I really do not understand what is the reason for that?

It looks like there is a zero also going lower frequence when the capacitive loading increase. This zero compensate the phase to have better phase margin.

Can anyone explain it for me or provide some material on that?

 

[maxwellequ]

Can you provide a schematic ?

 

[mike_bihan]

**broken link removed**

 

[maxwellequ]

The dominant pole is located at the output of the first stage, because that’s the high impedance node. The output node as low impedance due to the source follower.

The second pole (non-dominant) should be defined by the output resistance of the source follower and by your load capacitance. Therefore, increasing the load capacitance should worsen the PM...

The previous comments are true, unless you have a very big load capacitance, which would make the output pole dominant...

The schematic showing the way you are connecting the amplifier, to measure the ac parameters would probably help. And the value of CL, op data would also help...

 

[mike_bihan]

The big question was that why the zero is shifting with the change of output loading?

 

[maxwellequ]

I really do not see a reason to have a zero on the transfer characteristic (basically a zero occurs when there are two different signal paths with opposite signs that cancel each other at a certain frequency).

Without more data (operating point and incremental parameters values, load values, a schematic showing how are you making the feedback of the amplifier on your simulation) I cannot (try to) give you an answer.

Regards

 

[mike_bihan]

Let it be. Many thanks!

 

[vladimir1984]

dear mike_behan, I can you advise to read the amplifiers chapter in Jacob Baker 2-nd edition book, may help

 

[ccljpeg]

I advice you to read Allen & Holberg : CMOS Analog Circuit Design 2nd edition

 

[manissri]

ya gregorian and allen book is very good in this respect..