wlm model synthesis
Dear Friends,
I attended interview.I was asked this questions.I cleared interview but some of them i was unable to answer.Kindly answers for this questions.
1) what are advantages and disadvantages of TOP-Down and Down top synthesis Approach
small design, simple design, top-down
large design, designs with many clocks or other messy stuff, Down top
2) What is wireload model. what is advantage and disadvantages
Correct me if I am wrong.
For each wireload model, the synthesizer will select a set of timing/area/etc parameters to use during synthesis. Normally I give my design a free run to see the gate count then choose the next WLM larger than that. If unsure, set DC to auto.
3) what is set constant propagation
Correct me if I am wrong, when the input to a module is tied to constant, the synthesizer can remove some logic in the module.
4) what is boundary optimization
Correct me if I am wrong, when you use best-min library to fix hold time violation and worst-max lib to fix setup time? This is new to me though.
5) how to remove clock transition violations
is this done in P&R? you use larger clock buffers..
6) what is false paths and disable timing arc.What is affect of disable timing arc is a circuit is given
data path between two clocks is false path.
7) what is design ware components. why they are used .Advantages .disadvantages
they are optimized, and good designs. Advantage is you get good design and less code. Disadv is when you port to FPGA or using Cadence's synthesizer, you must code these designware yourself.
8) why primetime analysis will be done in best min and worst max conditions .why not best max and worst min.What happens in the latter cases
best min is the most probable senario for hold time violations to happen, worst max for setup.
I thought one need to do it in all 6 conditions and with parasitics?
9)Is it possible to fix hold violations by decreasing frequency.
No. it will fix setup time viols.
Rarely would one decrease clock frequency.. it's a fixed value since start.
10) what is constant propagation
go back to 3)
11) what is gated clocks .Advantages and disadvantages
for power reduction.
there are two kinds..
one for shutting down entier system, but you need good skills to synthesize/P&R them.
The other is register-level clock gating, there are some specific coding rules in RTL to enable synthesizer to insert clock gating to some registers. One simple example is
Code:
always @(posedge clk or negedge rst) begin
if (rst == 1'b0) begin
dat <= 10'd0;
end
else begin
if (sel0) begin
dat <= dat0;
end
end
end
12)what is DRC violation fixing. How you will do it.
There are so many rules in design compiler, max_capacitance, max_area, max_fanout, etc.. each has its own specific technique to fix.
Some can simply be waived during synthesis and let P&R take care of them.
Thanking you