I just trying to do 33% of duty cycle, but when I just run waveform, and my clock doesn't work........can u tell me how to solve it ???? thanks again!!!!!
Did I head the right way to this kind problem???
module div3_a(clk,clk_out);
input clk;
output clk_out;
reg [1:0] cnt_p, cnt_n,cnt_m;
wire [1:0] cnt_p_nx, cnt_n_nx,cnt_m_nx;
initial
begin
cnt_p = 2'b11;
cnt_n = 2'b11;
cnt_m = 2'b11;
end
assign clk_out = cnt_p[0] | cnt_n[0] | cnt_m[0] ;
assign cnt_p_nx = {cnt_p[0],~(cnt_p[0] | cnt_p[1] )};
assign cnt_n_nx = {cnt_n[0],~(cnt_n[0] | cnt_n[1] )};
assign cnt_m_nx = {cnt_m[0],~(cnt_m[0] | cnt_m[1] )};
always @(posedge clk)
cnt_p <= cnt_p_nx;
always @(negedge clk)
cnt_n <= cnt_n_nx;
always @(posedge clk)
cnt_m <= cnt_m_nx;
endmodule
This is my code for 50% of duty cycle,
module div3_b(clk,clk_out);
input clk;
output clk_out;
reg [1:0] cnt_p, cnt_n;
wire [1:0] cnt_p_nx, cnt_n_nx;
initial begin
cnt_p = 2'b11;
cnt_n = 2'b11;
end
assign clk_out = cnt_p[0] | cnt_n[0];
assign cnt_p_nx = {cnt_p[0],~(cnt_p[0] | cnt_p[1])};
assign cnt_n_nx = {cnt_n[0],~(cnt_n[0] | cnt_n[1])};
always @(posedge clk)
cnt_p <= cnt_p_nx;
always @(negedge clk)
cnt_n <= cnt_n_nx;
endmodule
---------- Post added at 10:47 ---------- Previous post was at 10:45 ----------
[/COLOR]Hello Mr.barry, I shouldn't be like that lazy.....I already do by myself!!!