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Question for Frequency divide by 3 of 33% and 50% duty cycle

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pig8190

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1. Design two frequency divide-by-3 circuits, one with output div3a (33% duty cycle), the other with output div3b (50% duty cycle). You can use rising-edge and falling-edge FFs in your designs.
Write the verilog code to generate div3a and div3b. Write a test fixture and capture the waveform. thanks!!!!!!!!
 

imbichie

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hi pig8190,

Its not a complex one you can do it yourself if you working hard....

After trying, If you don't get, please post your code with comments , then many of them are ready to solve your issue....

You can refer the below link....

https://www.edaboard.com/threads/48149/
 

pig8190

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I just trying to do 33% of duty cycle, but when I just run waveform, and my clock doesn't work........can u tell me how to solve it ???? thanks again!!!!!
Did I head the right way to this kind problem???

module div3_a(clk,clk_out);
input clk;
output clk_out;

reg [1:0] cnt_p, cnt_n,cnt_m;
wire [1:0] cnt_p_nx, cnt_n_nx,cnt_m_nx;

initial
begin
cnt_p = 2'b11;
cnt_n = 2'b11;
cnt_m = 2'b11;
end

assign clk_out = cnt_p[0] | cnt_n[0] | cnt_m[0] ;
assign cnt_p_nx = {cnt_p[0],~(cnt_p[0] | cnt_p[1] )};
assign cnt_n_nx = {cnt_n[0],~(cnt_n[0] | cnt_n[1] )};
assign cnt_m_nx = {cnt_m[0],~(cnt_m[0] | cnt_m[1] )};

always @(posedge clk)
cnt_p <= cnt_p_nx;
always @(negedge clk)
cnt_n <= cnt_n_nx;
always @(posedge clk)
cnt_m <= cnt_m_nx;


endmodule

This is my code for 50% of duty cycle,

module div3_b(clk,clk_out);
input clk;
output clk_out;

reg [1:0] cnt_p, cnt_n;
wire [1:0] cnt_p_nx, cnt_n_nx;

initial begin
cnt_p = 2'b11;
cnt_n = 2'b11;
end

assign clk_out = cnt_p[0] | cnt_n[0];
assign cnt_p_nx = {cnt_p[0],~(cnt_p[0] | cnt_p[1])};
assign cnt_n_nx = {cnt_n[0],~(cnt_n[0] | cnt_n[1])};

always @(posedge clk)
cnt_p <= cnt_p_nx;
always @(negedge clk)
cnt_n <= cnt_n_nx;

endmodule

---------- Post added at 10:47 ---------- Previous post was at 10:45 ----------

[/COLOR]Hello Mr.barry, I shouldn't be like that lazy.....I already do by myself!!!
 

nisshith

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much simpler code for
Divide by 3 clock with 33% of duty cycle
Try this one.

module div3_a(clk,clk_out);
input clk;
output clk_out;

reg reg_a, reg_b;
wire regb_in;

initial
begin
reg_b= 1'b1;
end

assign clk_out = reg_b ;
assign regb_in = ~(reg_b|reg_a);

always @(posedge clk)
begin
reg_a<=reg_b;
reg_b<=regb_in;
end

endmodule
 

imbichie

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Hi
Also this may works well

module div3a(clk,clk_out);
input clk;
output clk_out;

reg clk_temp[2:0];

initial
begin
clk_temp= 3'b100;
end

assign clk_out = clk_temp[2] ;

always @(posedge clk)
begin
clk_temp <= {clk_temp[1:0],a[2]};
end

endmodule
 

pig8190

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thanks so much for u guys help !!!! Really appreciate that !!!!
 

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