Question about Xilinx FPGA Editor

[EDA_hg81]

I have set timing constraint parameter,OFFSET OUT AFTER, with different values for the same net.

When I used FPGA editor to check, I found out the timing delay for the same net is same even I set OFFSET OUT AFTER with different values.

Do you think it is right?

Thanks.

 

[echo47]

It could be correct. Is it meeting your constraint?

Like most timing constraints, OFFSET_OUT_AFTER doesn't specify the time delay, it specifies the maximum time delay.

 

[EDA_hg81]

if it only specifies the maximum time delay.

how I can synchronize those output data?

Only thing I can do is to modify internal net time delay?

 

[echo47]

In general, you cannot specify absolute net delays.

The best way to minimize the skew between multiple output pins is to use the flip-flops in the IOBs. Their timing is much more predictable than routing the signals from somewhere in the logic fabric to the output buffers.

If your design can't use the IOB flops for some reason, then you may be able to carefully place your logic close to each IOB, thereby minimizing the delay and hopefully reducing the skew between multiple outputs.

Does anyone recall if ISE has a routing constraint that equalizes the delays among multiple signals? I vaguely recall seeing something like that long ago, but maybe not.

 

[nxtech]

Xilinx does allow you to control the timing of a group of signals but you have to group them together. This is detailed in the constraints editor users guide.

E

 

[EDA_hg81]

Yes, I have grouped my internal signals and output signals in Spartan 3.

My internal signal is the SDR and output is the DDR.

The SDR signal is synchronized with the system clock ( 14.65 ns ) and DDR is generated by system clock0 and clock180 ( 180 degree shifted system clock ).

The output downstream data is synchronized with second DCM Clock shifted certain degrees from system clock.

I have used “from to” constraints for synchronizing those two groups signals such as following:

TIMESPEC "TS_INTERNALTOOUT" = FROM "INTERNALDATA" TO "OUTDATABUF" 3 ns;

My question is Do you have any ideas

1) Which timing constraints ( “offset in before”, “offset out after” and “from to” ) generates Max time delay and which one generates Minim time delay?

2) Do you think my constraints for down stream DDR data is right?

NET "RSDS_OUT_GN<0>" OFFSET = OUT 3 ns AFTER "CLK_IN" HIGH ;
NET "RSDS_OUT_GN<1>" OFFSET = OUT 10.325 ns AFTER "CLK_IN" HIGH ;

In this case DDR clock is shifted ( 3ns + 3.6625 ns = 6.6625 ns) from the system clock.

By the way do you know any free timing digram editor?

 

[nxtech]

Before anyone can give you any suggestions on what to do we have to know what your overall timing budget is for your application.

To answer question 1. You cant specify min times in the literal sense, you can only specify a max time. The timing specs you put in are more like set up and hold times. This is because the tool cannot gurantee that if you specify a 10ns OFFSET in time that is can do it in say 5ns. It might be able to based on available routing resources and any other contraints.

For question 2, I cant say if those times look right or not without seeing the timing budget you have available from the time you need to access the DDR to the time you have available to either write to or read from the DDR. It will also depend on where in the FPGA your logic gets placed. If you can get your logic close to an I/O block you could be well in your budget, HOWEVER if your logic ends up in a part of the device that requires a long path to the output pins you could very well end up violating the DDR timing.

As for a free timing diagram editor, I am only aware of the one that is present in the ISE tool.

 

[EDA_hg81]

How I can check internal clock timing delay? ( I can check internal signal timing delay by using FPGA editor)

Using grouping method for internal signals ( using “From to” timing constraints) only can realize the time delay between two groups, we also need clock timing delay of those groups for checking setup and hold validation and setting signal timing delay.

I am really confused here.

Please let me know.....

Thanks.

 

[echo47]

Hi EDA_hg81, I'm looking at DDR.JPG, but I'm not clear what you mean by "downstream". Are you outputting two differential signals "Data out" and "DDR Clk" from the FPGA to another chip? That would explain your need for alignment between the two signals. You can use IOB DDR flops to generate *both* signals, and the resulting outputs will have pretty tight alignment. The DDR flop generating "DDR Clk" would also use CLK0 and CLK180, and you simply tie its two data inputs high and low.

Please clarify "internal clock timing delay". Delay from where to where?

 

[EDA_hg81]

outputting two differential signals "Data out" and "DDR Clk" from the FPGA to another chip

You are right; this is what I am doing.

I can shift the clock phase easily ( using DCM generator ) is the main reason why I used second DCM.

In my mind, if only one DCM is used then the Whole FPGA looks like a common clock system.

The data delay and clock delay are need for setting the correct set up timing for register to capture the data.
Setup margin = Clock delay- Datadelay
Right now I am confused how to check the clock delay in side FPGA.

 

[echo47]

"Shift the clock phase easily" -- are you attempting to output "Data out" and "DDR Clk" with a precise, adjustable delay between them?

"Register to capture the data" -- are you referring to a register in the external device that receives "Data out" and "DDR Clk"?

 

[EDA_hg81]

"Shift the clock phase easily" -- are you attempting to output "Data out" and "DDR Clk" with a precise, adjustable delay between them?

Yes. I want to get precise time delay between them.

"Register to capture the data" -- are you referring to a register in the external device that receives "Data out" and "DDR Clk"?

No. I am wondering how the registers inside FPGA can capture data correctly without validating setup timing.

Since the Whole FPGA looks like a common clock system/ System synchronize , How I can make sure the DFF can capture data correctly?

If DFF has setup time requriment, we have to check data delay and clock delay to make sure the setup timing is not validated.

 

[echo47]

I'm not sure what you mean regarding setup timing and capturing data correctly. If you specify a clock PERIOD constraint, then the synchronous logic using that clock will be routed to operate reliably at that clock period. If PAR can't meet your constraint for some reason, you'll get a timing error message.

This Verilog example synthesizes in ISE 9.1i for the Spartan-3 Starter Kit. It assumes a 50 MHz oscillator input. It generates two LVDS signals using DDR output flops: a pseudo-random data bitstream and a clock. Parameter "PHASE_SHIFT=26" delays clk0 by 2ns relative to clk, so it also delays the output clock signal by 2ns relative to the output data. The clock period is 20ns, so 20ns*26/256 = 2ns. (You can choose a different PHASE_SHIFT value.) The results look good in post-route simulation, and on my oscilloscope.

You may need to widen your web browser to avoid long-line wrap.

module top (iclk, odatap, odatan, oclkp, oclkn);
  (* LOC="T9", PERIOD="50MHz" *) input iclk;            // oscillator
                                 wire        clk;
                                 wire        clk0dcm, clk0;
                                 reg  [17:0] lfsr = 0;
                                 wire        odata;
  (* LOC="B10" *)                output      odatap;    // A2 pin 27
  (* LOC="A10" *)                output      odatan;    // A2 pin 28
                                 wire        oclk;
  (* LOC="A4" *)                 output      oclkp;     // A2 pin 18
  (* LOC="B4" *)                 output      oclkn;     // A2 pin 17

  BUFG buf0 (.I(iclk), .O(clk));
  FDDRCPE ff0 (.C0(clk), .C1(~clk), .D0(lfsr[0]), .D1(lfsr[1]), .Q(odata), .CE(1'b1), .CLR(1'b0), .PRE(1'b0));
  OBUFDS_LVDS_25 u0 (.I(odata), .O(odatap), .OB(odatan));

  DCM dcm1 (.CLKIN(clk), .CLKFB(clk0), .CLK0(clk0dcm), .RST(1'b0));
  defparam dcm1.CLK_FEEDBACK       = "1X";
  defparam dcm1.CLKIN_PERIOD       = 20.0;
  defparam dcm1.CLKOUT_PHASE_SHIFT = "FIXED";
  defparam dcm1.PHASE_SHIFT        = 26;    // clock 2ns after data
  BUFG buf1 (.I(clk0dcm), .O(clk0));
  FDDRCPE ff1 (.C0(clk0), .C1(~clk0), .D0(1'b1), .D1(1'b0), .Q(oclk), .CE(1'b1), .CLR(1'b0), .PRE(1'b0));
  OBUFDS_LVDS_25 u1 (.I(oclk), .O(oclkp), .OB(oclkn));

  always @ (posedge clk) begin
    lfsr <= {lfsr, lfsr[17] ~^ lfsr[10], lfsr[16] ~^ lfsr[9]};
  end
endmodule

 

[g0zde]

can anyone help me about my project which is about 64 bit carry look adder

 

[EDA_hg81]

I have read Xilinx white paper: What Are Period Constraints?

But I don’t understand the equations for the setup analysis and hold analysis.

In this paper:

Setup time = Data path delay + synchronous element set up time – Clock path Skew

But I think it should be:

Setup time = Clock path Skew – (Data path delay + synchronous element set up time)

And in this paper:

Hold time = Clock path Skew + synchronous element hold time – Data path delay

But I think it should be:

Hole time = Data path delay – (Clock path Skew + synchronous element hold time)

How do you think?

https://obrazki.elektroda.pl/55_1183857705.jpg

 

[echo47]

Your equations and Xilinx's equations differ only in the +/- sign of the answer.
It's probably just different perspectives of which direction is positive or negative.