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question about voltage headroom

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Full Member level 5
Oct 5, 2009
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i am having a hard time to understand what a voltage headroom is.

i am comparing the voltage headroom of a system using a single MOS current source as compared with the improved (cascode) current source.

Any idea and help will be appreciated.

The primary issue for a current source is its fidelity to the
master reference current. You have a Vds dependence
inherent to the MOSFET, from both the transition between
linear and saturation and from short channel effects.

Headroom goes more to the former. If the reference
device is a simple VDS=VGS MOS diode, then the current
source will dead-match only at VDS=VGS (Vbias), be
higher than reference at higher Vds (maybe not by
too much,
as long as you're not talking high accuracy requirements)
and lower at low Vds and much more so, because it is now
just a crudely controlled resistor. That's where your headroom
bind comes - gm*Rout just went in the tank, bias current
is below setpoint, all kinds of fun.

Cascodes enforce drain voltage matching on the lower,
"mirror" FETs and this is good. But once the guard FET loses
-its- VDS, that falls apart and the sensitivity comes right
thank you very much for the reply.

correct me if i'm wrong, my idea of voltage headroom is, it is a some kind of margin wherein a signal can swing properly,
for example, if i have a 2 volts output in the load of my single NMOS current source, the signal can swing properly within the 2-Vdsat range, while if its connected with the improved current source, the signal can have a swing of 2-2Vdsat.

that's why improved current source has that disadvantage as compared with the single one..

i got confused is voltage headroom some kind of a voltage drop? or is it the supply-drop?

It depends on the circuit and its "values" - a regulator
output stage might have a load current, I*R headroom
which is a "can't get there from here" sort of limit. But
a precision circuit has more subtle demands, at perhaps
an earlier (more headroom-demanding) point (you are
going to lose linearity or fidelity well before you hit the
brick wall).
with that, can I conclude that the improved current source has a voltage headroom problem as compared with the single current source?

It (the simple one) will be "roughly right" to a lower voltage
but the cascoded ones will be more accurate over a wider
voltage range.

If you used a replica of the output as feedback you could
extend the range of "good enough" in the cascoded mirror,
but that will require gain and frequency-stabilization.

If your process has "intrinsic" (VTH~0) FETs available
then you can use these for the cascode guards and get
nearly the same headroom as the simple version.

A source-degenerated mirror can produce nearly as good
flatness / linearity as a cascoded mirror, at the cost of maybe
100-200mV headroom (the degeneration pedestal voltage)
and possibly better matching, but it will cost you the area
of a high value resistor per FET.

thank you for the reply.

honestly, i still got confused about this voltage headroom.
i thought it was as simple as saying that, the improved current source consumes twice as what the simple current source does.
that's why the resulting swing has been reduced.

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