Question about timing check when do gate-level simulation

[xiaojigao]

When doing gate-level simulation with SDF annotated, we can use options to tell simulator use minimum, typical or maximum values specified in file.sdf be annotated on the design. My question is, does this option effect which value (min/typ/max) should be used for timing check in SDF?
For example, if there are below two lines in SDF:
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(IOPATH A2 ZN (0.095::0.107) (0.113::0.138))

(SETUP (negedge D) (COND ENABLE_RDN_AND_NOT_SE===1'b1 (posedge CK)) (0.174::0.175))
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When I add a optipn +maxdelays to simulator, in order to use max value when simulate delay, simulator will use "0.107" for A2 to ZN 0->1 delay, and "0.138" for A2 to ZN 1->0 delay.
My question is that, does this option "+maxdelays" also effect which value should be choosed for timing check(setup check in this example)? If it does, which value will be selected ? "0.174" or "0.175" ?
In my opinion, mix/typ/max means three process/operating conditions, if delay is maximun value, then timing check should choose minimum value for setup check. For example, if I add +maxdelays option to simulator, delay should use "0.107" for A2 to ZN 0->1 delay, and "0.138" for A2 to ZN 1->0 delay. And "0.174" should be used for setup timing check in this example.
Am I right?

Thanks a lot!