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question about the result of the output of the modelsim

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wqy1985

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I am studying a digital filter(used in a sigma-delta ADC). It is a multistage filter. I use the FDATool in matlab to generate the code of all the filter. And then I use the modelsim to simulate. But I can't understand the result(it looks like it will always increase(positive and negative alternatively)) which I will attach below(I plot some points of the results in matlab). the input is 4bits, output is 24bits, input signal frequency is 6.144MHz, decimation factor is 128. I attach the whole design below(including the verilog code, testbench, and mytestbench(I imply a sine wave)). Hope someone give me some clue.

thanks in advance.
 

wqy1985

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This is the result of the filter using mytestbench
 

wqy1985

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This is the result of the filter using the testbench which is the matlab generate automatically
 

tariq786

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I assume you have xilinx ise 10.1 or some other version. Why dont you go through the following way.
I have done filter design this way. I mean you generate filter coefficients in matlab and then import the coefficients file in xilinx ise using core generator.

Take a look at the following tutorial.Its long but useful.Do look from pages 21 and onwards.

https://www.xilinx.com/ipcenter/catalog/logicore/docs/da_fir.pdf
 

wqy1985

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what I mean is if I apply a signed 4 bits sine wave(which is generated by matlab)to the filter, is the output a 24bits sine wave as well?
 

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