Question about the gain of CMFB amplifiers

[discover_AMS]

Hi all

I am working on LVDS tx in 130nm technology for transmitting 250Mhz clock (Schematic enclosed)

I have a Query regarding Gain of CMFB amplifiers
According to Common mode & differential mode output swing Specification I decided
The transistor sizes of output switching network

Now MN2 size comes out to be very high & MN2 Cgs = 992.2920f & cgd = 91.2043f

For MN2 gate drain capacitance nearly equal to
Cgd + Cm = Cm = suppose I take 3pf

Total capacitance seen on gate source of MN2 is
Cm / (1-Av) + Cgs which is nearly equal to Cgs
Hence bias current should be decided by Cgs & slew rate of CMFB ckt
I = Cgs * dV/dt

How much slew rate I can take 4 this CMFB ckt ?
Only thing I m observing here that if I used lower bias current CMFB ckt hence it is very less 2 drive out huge MN2 current sink
CMFB transistors sizes are also large ???

Please help me.
Thanks & regards
Sunil

 

[avt]

Re: help in LVDS Tx

how did you size MN2 ?

 

[bluesmaster]

Re: help in LVDS Tx

what is your value of lp&cp&cl?

 

[avt]

Re: help in LVDS Tx

well, you can assume cp to be the bondpad-capacitance (something between 1pF and 5pF should be ok - 5 pF is alrady quite etreme - think about the impedance 1/2*pi*f*cp at some 100 MHz - this competes than already quite clearly with the termination)

anyway lp is the inductance because of bondwire etc - around some nH (5 ?) ...

cl is the load capcitance - normaly assumed also to be in the few pF-range ...

only a real package model and a rc-extraction out of the layout will give you more insight ...

when you have a package model than you might also get a glimpse how coupling inductances between adjescent lines might influence the output pins - and then thinks are getting quite evolved