Question about synthesis for FPGA and ASIC....

[dexter_ex_2ks]

Hello , I have a few questions:
1. Is there a difference between ASIC and FPGA synthesis ? (I know the differences between these two I.C.-s but to be more specific, from RTL to gate level,the compiler will synthesis in two different ways dending upon resources from the IC in the FPGA case?)
2. I've downloaded iverilog and vvp and gtkwave, my question is when I do the synthesis ( with -S ), I'll get a net-list, haw can I read this net-list more easily, is there an application (I need to see the schematic after synthesis), for study purpose.
A know that there is a trial from Xilinx, but but I'm low on resources, and that program needs ≈ 5GB hdd space. (more questions to come....)

Thanks in advance 2 all !
HAVE A NICE DAY !!!

Dexter

 

[ljxpjpjljx]

FPGA is synthesis for the target gates: LUT.......

 

[jbeniston]

Hello , I have a few questions:
1. Is there a difference between ASIC and FPGA synthesis ? (I know the differences between these two I.C.-s but to be more specific, from RTL to gate level,the compiler will synthesis in two different ways dending upon resources from the IC in the FPGA case?)

Yes - you'll need different tools.
FPGA synthesizers target LUTs and the odd macro (RAM, multipliers), ASIC synthesizers target standard cell libraries. Also, in ASIC synthesis, you may want to perform scan insertion, which you don't need to do for an FPGA.

 

[santhosh007]

you can view the schematic in debussy .. after loading netlist and corresponding libraries....