microe_victor
Junior Member level 2
A asynchronous FIFO requires synchronizing the write_pointer and read_pointer to the other clock domain for compare.
we compare syn_read_pointer and write_pointer to generate "full signal" , but the syn_read_pointer is not "latest" but 2 clock cycles before . so the "full signal" will be announced for the extral 2 cycles
Do this effect the efficiency of the fifo ? or do I misunderstand something?
please make some comments. thank you
we compare syn_read_pointer and write_pointer to generate "full signal" , but the syn_read_pointer is not "latest" but 2 clock cycles before . so the "full signal" will be announced for the extral 2 cycles
Do this effect the efficiency of the fifo ? or do I misunderstand something?
please make some comments. thank you