gggould
Member level 3
Hi,
Couple of questions about jitter peaking. My understand is it comes from insufficient PM around Open Loop Transfer Function zero crossing, which is about the PLL loop bandwidth. Am I correct?
But typically how do we address the peaking problem? Some paper says lowering wz/bw, other says it is a function of damping factor and fz/fp. I am not sure what is right / does people typically do.
For TYPE II 3rd order PLL, the pole zero location should be like
wp_dc_vco=wp_dc_LF->wz1_LF->wbw_pll=zerocrossing->wp1_LF?
Regards,
gggould
Couple of questions about jitter peaking. My understand is it comes from insufficient PM around Open Loop Transfer Function zero crossing, which is about the PLL loop bandwidth. Am I correct?
But typically how do we address the peaking problem? Some paper says lowering wz/bw, other says it is a function of damping factor and fz/fp. I am not sure what is right / does people typically do.
For TYPE II 3rd order PLL, the pole zero location should be like
wp_dc_vco=wp_dc_LF->wz1_LF->wbw_pll=zerocrossing->wp1_LF?
Regards,
gggould
