Question about Nytes in Verilog code of USB2.0

[bitblue]

When I am reading the Verilog code of USB2.0 device controller, I have a question.
The Rtl code is as follow:
`C_EP0_DA_OWDA: begin //this state is to wait the out data
if (((RxData0 & DataTog) | (RxData1 & ~DataTog)) & CSR0[0])
NextEP0State = `C_EP0_DA_OTRNT; //Nyet
else if ((RxData0 & DataTog) | (RxData1 & ~DataTog))
NextEP0State = `C_EP0_DA_OTRAK;
else if ((RxData0 | RxData1) & CRC16Good & RejectPacket)
NextEP0State = `C_EP0_DA_OTNAK;
else if ((RxData0 | RxData1) & CRC16Good)
NextEP0State = `C_EP0_DA_OTNYT;//Nyte
....
I can not understand the difference of those two Nyte. The first Nyte maybe is indicating that there are not enough space in the endpoint for the next out transfer ,but how is the second Nyte's function? so I wonder whether some friends who are familiar with USB2.o can ask my question. Thanks a lot

 

[mallikmarasu]

Re: about USB2.0

hi,
can u send the code of usb 2.0 device controller
i am working on wireless usb which is like as usb 2.0 added some features to usb 2.0 .so i want usb2.0 code .can u send that one.
that is very helpful for me to design my block


regards,
Mallikarjun,
Design Engineer.

 

[VSMVDD]

Re: about USB2.0

the ' may mean data at address... like a $ in c
so its just seeing if there is data and

if there in anything but zero

make the first variable equal to it

used by fifo etc...