question about low power CTS

[drizzle]

Although primary power consumption reduction can often be realized by method such as clock gating taken by front end designers, we can still reduce it during CTS.

One method to decline the power consumption is to weaken the skew and delay penaltyand then double-spacing clock nets routing,which pehaps occers in deeper nanometer design.

anybody can explain about " double-spacing clock nets routing"?
what it will benefit for?

thanks

 

[eternal_nan]

Double spacing clock nets will decrease the amount of parasitic capacitance being driven by the clock tree (capacitance to neighboring traces, dominant in smaller geometries is reduced because of the added distance) and P ~ C*F*V^2

 

[spauls]

Signal integrity and noise effects will be taken into care while spacing.