hawk
Member level 4
verplex-LEC-Q
Hi fox,
I have a Q regards to LEC:
in the golden RTL I have put the following code-
always @(posedge clk or negedge rst_n)
if !rst_n
........
In the gate level (revised section) I have uploaded DFF With active low rst.
When i run compare in LEC, i got error on the rst path, regards to active low.
In the RTL section i got a not gate & in the gate level i didnt.
So.... this cause a functionality missmatch, which is not correct.
because the tech lib have an active low rst FF's.
Need your help to tell LEC how to deal with this.
Hawk.
Hi fox,
I have a Q regards to LEC:
in the golden RTL I have put the following code-
always @(posedge clk or negedge rst_n)
if !rst_n
........
In the gate level (revised section) I have uploaded DFF With active low rst.
When i run compare in LEC, i got error on the rst path, regards to active low.
In the RTL section i got a not gate & in the gate level i didnt.
So.... this cause a functionality missmatch, which is not correct.
because the tech lib have an active low rst FF's.
Need your help to tell LEC how to deal with this.
Hawk.