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How much time does it take to run and get the desired results for a gate-level netlist simulation compared to building a LEC script and running it? Have you considered that factor?
When LEC fails, debugging can be a pain in the ass. Sometimes you get 5 gates that do not match in an unrelated part of the circuit. Sometimes you get 100Kgates do not match spread all over. Some of these patterns are very easy to spot via simulation.
Also, gate level sim does not always take power ports into consideration, so LEC can help with making sure your VDD does not mix with your other VDDs or GNDs.
All in all, both are verification routines. When you are doing a million dollar tapeout, you better spend time doing both and doing it well.
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