Question about Hold Time violation

Hold Time Issue!!??

Hi all,

I understand that Hold time violation happens when the data retain too short after the active edge...

But what about, say the data retain for 2 clock cycle, but it falls on the 2nd active edge, does this still consider hold time violation!!??

If yes, so how could I solve the hold time violation for this data signal which comes from external module(Micro-controller), which is not synchronize with the FPGA design clock, but both having same clock frequency(50Mhz).

Thank you for reply and advice.

Regards,

Re: Hold Time Issue!!??

If you are using xilinx FPGAs, you can add delay for input signals in the IOBs to meet your hold time requirements.

Re: Hold Time Issue!!??

It can cause Hold time violation.
To avoid this put synchronizers.

Re: Hold Time Issue!!??

Hi,

The probelm with hold (or setup) time violation is that the output of your flip flop mayu not be at the expected value. So you should consider this output as invalid.
If your input signal stays for 2 clock cycles, and if you can know when the input changes (may be with chip select signal ...), you can use the output of your flip flop only after the first clock , and ignore if for the second one.
Build a small state machine for this data validation system.

I hope this will help you.

:wink:

Re: Hold Time Issue!!??

Hi all,

Thank you for reply, very appreciate..

I'm using Alter@ Fpga and Qu@rtus II v2.2, can you please tell me how should i fix the hold time violatatin from the input port.


Secondly, how could I synchronize with the external module, since the external clock is not going to the FPGA!!?

Regards,

Re: Hold Time Issue!!??

As the external clock and the internal clock are both operating at same frequency (50MHz) and the data is retained on the bus for 2 clocks, the best way to operate is to latch the data on the first clock cycle if you are having hold time issues as in r_e_m_y's post.

I dont know if @ltera supports, if it does, delaying data bus in the IOBs with the period by which it is missing the hold time.

Re: Hold Time Issue!!??

If i understand your question correctly, asynchronous fifo maybe a better choice. If you use a 50M clock to sample a signal generated by another 50M clock, you have a high chance to lose data.

regards

Re: Hold Time Issue!!??

Hi all,

what about now the external module data only retain for 1 cycle, is there any method to avoid meta-stable of the FPGA register??

Regards,
always@smart

add one register

Re: Hold Time Issue!!??

See the Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs on by Clifford E. Cummings. This paper is available for download at https://www.sunburst-design.com/papers/
He explanes "metastability" and "synchronizers"

best reards
vladz

Re: Hold Time Issue!!??

Answer for your question depends on clock sources used in data source and data destination:
- if it is the same clock, with some latency in between, you could try to play with (I work with Xilinx FPGA) feedback for clock de-skew in internal PLL and add/remove delay in IOB to compensate this latency (by the way, in PCB design clock is supposed to be routed to avoid those latencies)
- if those two 50MHz clock are generated independently you could treat them as asynchronous clock sources and do real synchronization (Cumming’s paper is definitely best source which cover this)
If you could, instead of simple flop, on destination side to qualify sampling only to first clock edge, where data is stable, it is of course the simplest way to solve this.