What I want to do is as follow:
The gate of MOSFET is controlled by FPGA at a certain time. Before this certain time I do not want any glitch shows on the drain of MOSFET since this glitch can trigger circuit to operate at wrong timing.
But when power on the whole system, the glitch shows on the drain of MOSFT
which is unavoidable
So I try using Schmitt trigger to block this unavoidable glitch.
The question is if Schmitt trigger can generate another unavoidable glitch when power is on?
Thanks.