Question about glitch again

[EDA_hg81]

When power is on the drain of MOSFET generates a glitch ( 10V around), which is unacceptable and unavoidable .

I plan to use a Schmitt trigger to block this glitch. But I am wondering if the Schmitt trigger can generate another glitch?

Thanks

https://obrazki.elektroda.pl/70_1187705859.jpg

 

[A.Anand Srinivasan]

the capacitor doesn't allow sudden change in voltage and hence it would take care of smoothening the glitch but usage of schmitt trigger makes it even better....

 

[Iouri]

OK hold on a second. What exactlly you are trying to do?

 

[EDA_hg81]

What I want to do is as follow:

The gate of MOSFET is controlled by FPGA at a certain time. Before this certain time I do not want any glitch shows on the drain of MOSFET since this glitch can trigger circuit to operate at wrong timing.

But when power on the whole system, the glitch shows on the drain of MOSFT
which is unavoidable

So I try using Schmitt trigger to block this unavoidable glitch.

The question is if Schmitt trigger can generate another unavoidable glitch when power is on?

Thanks.

 

[A.Anand Srinivasan]

most circuits come with a power on reset(POR) circuit which resets the whole circuit after power on and if your FPGA has such a circuit embedded then there wont be a problem... using a capacitor is a better solution when it comes glitch because it smoothen the glitch due to the time required to charge it....

 

[Iouri]

and what is output of the MOSFET or Schmidt trigger suppose to drive?