jojo12520
Newbie level 5
verification_set_undriven_signals
When I use synopsys's tool FORMALITY to do formal verification of a module's RTL2NL( the netlist is generated by DC's command "compile_ultra"),it have several aborted points, the reason is too complex to resolve. And it takes very long time to finish the verify. Is there any good resolution?
Thanks
When I use synopsys's tool FORMALITY to do formal verification of a module's RTL2NL( the netlist is generated by DC's command "compile_ultra"),it have several aborted points, the reason is too complex to resolve. And it takes very long time to finish the verify. Is there any good resolution?
Thanks