bdatta
Newbie level 4
Hello
i am working on a test-chip using ibm-soi 45nm design kit provided by MOSIS. We are not packaging our die. Currently i am working on making the pads. I have decided on making them 100 x 100 micron sq since that will ensure sufficient landing area for any type of probe we use (ac or dc). I had a query: should i be creating metal blocks right from M1 and continue placing blocks one on top of another with via arrays till the topmost layer OR just do that for the top-3 layers and simply have connecting vias to the I/O buffer then on.
Any help will be greatly appreciated.
Thanks
Basab
i am working on a test-chip using ibm-soi 45nm design kit provided by MOSIS. We are not packaging our die. Currently i am working on making the pads. I have decided on making them 100 x 100 micron sq since that will ensure sufficient landing area for any type of probe we use (ac or dc). I had a query: should i be creating metal blocks right from M1 and continue placing blocks one on top of another with via arrays till the topmost layer OR just do that for the top-3 layers and simply have connecting vias to the I/O buffer then on.
Any help will be greatly appreciated.
Thanks
Basab