i am working on a test-chip using ibm-soi 45nm design kit provided by MOSIS. We are not packaging our die. Currently i am working on making the pads. I have decided on making them 100 x 100 micron sq since that will ensure sufficient landing area for any type of probe we use (ac or dc). I had a query: should i be creating metal blocks right from M1 and continue placing blocks one on top of another with via arrays till the topmost layer OR just do that for the top-3 layers and simply have connecting vias to the I/O buffer then on.
Any help will be greatly appreciated.
all metal must be used to have strongest area, if you have enought place.
when you indicate 100ux100u, you did not say the bond pad is require this huge area?
Hi
Thanks for your reply. This is not for a bond pad as i have mentioned we are not packaging. This is a regular probing pad, we will be using our own test equipment to do the measurements. I basically wanted to know whether i should construct a metal skyscraper or do i simply draw a rectangle of the top metal layer & then drop to M1 using vias to connect to the I/O buffer (this i believe might have reliability issues).