Question about Configuration Specification

[jianhuachews]

hi guys.. I have 3 separate programs now and they are a seven segment decoder, a 4bit up down counter and a frequency divider.

I need to combine these merge these 3 programs using configuration specification however i'm very lost when i tried doing it. I read up online sources but i could not understand, still.

This is what i tried doing, ok but i very sure it's wrong. And there's a fatal that states "unexpected signal:11"

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

entity counter_top is port (
		clear, updown, load, enable, clk: in std_logic;
		data_in: in std_logic_vector(3 downto 0);
		d1: out std_logic_vector (6 downto 0);
		g1, g2, g3, g4: out std_logic
);

end; 

architecture behavior of counter_top is 

component seg7 port (
	I : in std_logic_vector(3 downto 0);
	seg : out std_logic_vector(6 downto 0)
);
end component;

component counter port (
	en,clk, clr, up_down, ld : in std_logic;
	din : in std_logic_vector(3 downto 0);
	Q : out std_logic_vector(3 downto 0)
);
end component;

component freqdiv port (
		input_clk: in std_logic;
		output_clk: out std_logic
);
end component;

[COLOR="#FF0000"]signal clkdiv_out: std_logic;
signal seg_out: std_logic_vector(6 downto 0);[/COLOR]


begin
g1 <= '0';
g2 <= '1';
g3 <= '1';
g4 <= '1';
[COLOR="#FF0000"]I1: seg7 port map (ld=>load, en=>enable, up_down=>updown, din(3)=>data_in(3), input_clk=>clk, clr=>clear, output_clk=>clk, Q(3)=>I(3), seg=>seg(6));

I2: seg7 port map (ld=>load, en=>enable, up_down=>updown, din(2)=>data_in(2), input_clk=>clk, clr=>clear, clk=>clkdiv_out, Q(2) =>I(2), seg=>seg(5));

I3: seg7 port map (ld=>load, en=>enable, up_down=>updown, din(1)=>data_in(1), input_clk=>clk, clr=>clear, clk=>clkdiv_out, Q(1) =>I(1), seg=>seg(4));

I4: seg7 port map (ld=>load, en=>enable, up_down=>updown, din(0)=>data_in(0), input_clk=>clk, clr=>clear, clk=>clkdiv_out, Q(0) =>I(0), seg=>seg(3));

I5: seg7 port map (ld=>load, en=>enable, up_down=>updown, din(0)=>data_in(0), input_clk=>clk, clr=>clear, clk=>clkdiv_out, Q(0) =>I(0), seg=>seg(2));

I6: seg7 port map (ld=>load, en=>enable, up_down=>updown, din(0)=>data_in(0), input_clk=>clk, clr=>clear, clk=>clkdiv_out, Q(0)=>I(0), seg=>seg(1));

I6: seg7 port map (ld=>load, en=>enable, up_down=>updown, din(0)=>data_in(0), input_clk=>clk, clr=>clear, clk=>clkdiv_out, Q(0)=>I(0), seg=>seg(0));

d1<=seg(0);
[/COLOR]
end behavior;

configuration cc of counter_top is
for behavior
[COLOR="#FF0000"]for all: seg7 use entity work.seg7(behavior);[/COLOR]
	end for;
end for;
end cc;

Re: Im having trouble with the part in red!!

 

[sanju_]

hi
i too lost in your code
here in your code
"component seg7 port (
I : in std_logic_vector(3 downto 0);
seg : out std_logic_vector(6 downto 0)
);
end component;"
it declares only two ports 'I' and "seg"
but below code declares more than two ports
"I1: seg7 port map (ld=>load, en=>enable, up_down=>updown, din(3)=>data_in(3), input_clk=>clk, clr=>clear, output_clk=>clk, Q(3)=>I(3), seg=>seg(6));"



even i am not good in configuration but see the syntax below
VHDL Reference Guide - Configuration Specification
**broken link removed**