Question about CML divider

[siboy]

cml divider

I made a CML divider. It can easily work up to 4GHz @tt. But when I change the section to ss, it doesn't work anymore. Even I reduce the input freq to 2GHz/1GHz/500MHz or increase the current, it doesn't divide. I guess the problem maybe oscillation startup, so I increas the simulation time and improve the simulation presicion. But this doesn't have any effect.
Does anyone met this problem?
What should I do?
Thanks!

 

[Teddy]

cmos cml divider

a) what is your voltage swings?
b) how do they change from tt to ss

 

[siboy]

cml cmos divider

Thank you!
The output voltage swing is 400mVpp.
The divider doesn't work @ss, its output swing is only several mVpp. So how can I make it work @ ss?

 

[jjx]

cml divider 4ghz

Some additional questions:

* Is your tail current dependent on the resistive material?
* Do you look at only one stage (how many do you have) when you say it doesn't work?
* How do you drive the input(s)?
* What is the supply voltage (to refer to 400 mVpp)
* CMOS or bipolar?

 

[siboy]

current mode logic divider


My divider is a normal CMOS cml divider formed by two cml latch. The tail current is a normal CMOS transistor. I used 2 CML buffer as the load. I used another CML buffer to drive the divider. VDD is 1.8V, and the input of the CML divider is about 400mVpp. The divider can work with 200mVpp input swing @ tt.

 

[jjx]

divider frequency cml current

OK,

so no PMOS in the circuit, i.e., slow NMOS is the problem. I guess you would see the circuit not passing in slow-n/fast-p too (dependent on corners characterization of course, I suppose the resistance is changing too dependent on material).

Are the resistors ideal or poly-something material in your test bench?

I also guess you define the tail current by using an ideal current source through a current mirror in your test bench? Can you instead make the current dependent on a resistance - using same resistive material as in the load resistors - to make the swing independent of corner (and temperature) - one needs to guarantee that the swing does not get too large either?

I also guess you have investigated the voltage levels after and before the buffer stages and checked that the signals don't die already there?

Since you have reduced the frequency that much in your tests and circuit still not working I would think that the transistors are somehow cut-off. (With really slow frequency the outputs should settle to a value R*I as peak voltage - otherwise current is disappearing somewhat odd).

You mention that you have increased the current and then you would effectively increase voltage across resistors and push down the input voltage further to the input stage. That in combination with slow nmos transistors that increases the required VGS /VDS would make the block poorly conditioned. (What happens if you decrease the current?)

Are you measuring the swings differentially or/and have you checked the single-ended swing and levels?

 

[jecyhale]

cmos cml divider

I made a CML divider. It can easily work up to 4GHz @tt. But when I change the section to ss, it doesn't work anymore. Even I reduce the input freq to 2GHz/1GHz/500MHz or increase the current, it doesn't divide. I guess the problem maybe oscillation startup, so I increas the simulation time and improve the simulation presicion. But this doesn't have any effect.
Does anyone met this problem?
What should I do?
Thanks!

Try to use the constant idea current source and double the MOS size.

If it can't work, please check the model with foundry.