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Question About Clock-tree Synthesis!

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Junior Member level 2
Sep 19, 2002
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Anyone familiar with Clock-tree Synthesis(CTS)?
Suppose a gigantic SoC design case, there are a RISC cpu core and a number of other sub-modules in it. Then how do you build the Clock-tree?
Do you build Sub Clock-tree within(in) the sub modules or only do CTS from the top-level?
In our design case, we do CTS from top-level using SE(Ctgen), and i feel that too many clock-buffers are inserted in front of the sub-modules so the clock-insertion-delay is so large.
Would you tell me how do you do it in this case?
And do you do it automatically with CTS tools or ...?

Why nobody say something?

For a bigger design, the larger delay of clock tree is inevitable,
but it doesn't matter, the most critical issue is skew, not delay.

For SE CTS, if it cannot meet the minimum skew, it must increase
the delay.

If you have inhouse clock tree design rule (the rule must be
enforced by some inhouse tool to check it). You can split your clock
tree into subtrees then do the highest level by "hand", if you don't have
the rule, you better do everything by tool.

by the way, which version of SE/CTS you used? i don't know
the performance of latest release, but the one in SE5.0/5.1 is not good
for bigger design. You may compare with Astro or Celestry's tool.

Thank you for you advice.
We use SE5.4.

From my pass experience...
While Astro come to the problem that it can not fix all the voilations, it will do some stupid job such as put buffer in series. End up, it might bring bad result.

One you can do if you are using avanti is to run Jupiter CTS in explorer mode over your whole design and it will run through a bunch of algorithms and suggests the best CTS implementation for your design. Usually it comes close to an optimal CTS solution. Then, you read the generated report and pick the best one. Feed this into CTS to generate your tree.

All clock balanced tool tended to over design. (not all the flops talk to each other. For example, when will a debounced flop on your GPIO talk to your flops in memory controller? but tools balanced their skew!!!) That's the reason why you will see huge delay on the clock tree.

I prefer you can manully route clock to different part of the chip ,especially around hard macro. Otherwise clock matching of different brance will cost you too much time.

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