question about area after synthesis

[moon91]

What should I do if I find out the area after synthesis is larger than I expected?
(this is a question that I encountered during an interview, can any one help me find the answer? Thank you )

 

[Dar89]

I don't know the answer, but i would check:

1) the correctness of the RTL description
2) How the datapath blocks have been implemented
3) If I have imposed the correct timing constraints (obviously area is strongly dependent on the timing constraints that you impose).

 

[biju4u90]

From my very limited knowledge on synthesis, I can say this.
You can add some area constraints like set_max_area during synthesis. There is a trade of between area, delay and power and to reduce area, you have to compromise on the others. Another method could be changing the effort level to low so that delay will be increased, but area and power could be reduced. I don't know if there are other better methods.

 

[moon91]

Hi, thank you for your help. I was wondering that could you give me some examples about the timing constraints you talked about in point 3?

 

[moon91]

I don't know the answer, but i would check:

1) the correctness of the RTL description
2) How the datapath blocks have been implemented
3) If I have imposed the correct timing constraints (obviously area is strongly dependent on the timing constraints that you impose).

Hi, thank you for your help. I was wondering that could you give me some examples about the timing constraints you talked about in point 3?

 

[artmalik]

I am not sure if the question is valid one at all. the idea of synthesis is not get an area but convert the RTL into gates. The idea is to get a reasonable gate count or rather gate types(like the kind of flops you are using multi-bit or single bit). This is important because of the tools like P&R or timing will upsize/downsize the gates as needed. They don't do much of gate level optimization.

Area will be impacted more by P&R. But if your area is large then either your estimation is wrong or your constraints are wrong. Constraints will be clock frequency, choice of stdcell libraries, Vt of the devices used, aspect ratio of the estimated block area....