Query regarding Routing of DDR3 Data Byte

[Anonymous_Ricky]

Hi All,

How critical it is to route all Data Group signals in one layer.
Suppose, if I route mask and strobe in one layer and rest of Data Byte in other layer maintaining the recommended spacing will that effect the signal integrity.
I have very tight space constraint and I have to do this to get enough space for length matching.


Regards,

Ricky

 

[cks3976]

If this is an impedance controlled PCB then there is no need of routing the complete bus in one signle layer. In fact that will be very difficult to accomplish. And you have also mentioned about length matching. I suggest you to google this forum for routing guidelines for DDR-3. layout recommondations for DDR-3 are much relaxed than DDR-2

 

[otherguy]

You can also look at swapping the data pins within a byte to ease length matching.

 

[Anonymous_Ricky]

I have already tried swapping.
@cks3976 Yes board is impedance controlled and I have searched some documents but each recommends that it should be routed in single layer.
What I like to know is has anyone done that before in any boards with DDR3 working properly after that.

Thanks,
Ricky

 

[otherguy]

I've never done it and I've never seen it done. If you need to, I'd match the lengths as close as possible and use layers that are close to each other so that capacitive delay through the via will be similar. If you are able to account for that delay in the length match, that would be best.

I wouldn't worry too much. I've seen really poorly routed and length matched DDR2/3 and it still "works". You just might have to run it at a slower speed.

Do a simulation if you want to cover your *ss.

 

[marce]

We always do simulations on DDR interfaces, as Otherguy as said its the best way to cover yourself, and in the longrun its better to simulate and get a working board, than try and second guess what is going to happen.