Ravinder487
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@steadymindwhat exactly are u trying to achieve.....
Thanks steady mind,I could get something from your explaination but not complete.Again my question is will an OTA with 190MHz GBW can sample signal in 1nS?? Sorry to ask same question again and again but I couldn't get clear picture !!if ur OTA can sample ur input to Ch withing 1nS (0.5*Ts) with error less than (25% of 18mV -- as much as u allocate) then u are fine..
I've simulated with input frequency of 2MHz output exactly follows input but for 200MHz signal output isn't near replica for input.What are the things that I need to do to improve its performance.OTA with 190MHz GBW has to respond as fast as your input signal within 1nS time frame, try simulating this.
Sorry!! I couldn't get the meaning of hold caps.If possible can you try to explain with timing diagram.i use the caps in the the DAC to be hold caps during the Vin sampling phase. I have a buffer (ota) which will be able to drive the caps in the dac to Vin with the sampling time within error limits .
Yeah I've changed complete OTA,increased sizing of first stage so as to increase slew-rate but their sizing are coming to be very huge(80u).Now my OTA settling time is around 4ns(still doesn't reach my specs).output slew-rate isn't the same for both rising and falling(WHY??) and I do observe that there are overshoots when output it is going low and no overshoots when it is going high(??)for 200MHz input signal u need a bandwidth of atleast 200MHz, so increase ur OTA bw else roughly find out at what input freq ur output is different from input for 190MHz OTA. then u can scale ur OTA bw to match ur input sampling freq.
I think I need to detach buffer from DAC while it is sampling as the capacitors will be performing DAC operation(??)If this is true then how can I accomplish this taskdirectly buffer(unity gain OTA) to drive the input voltage on these caps
How can I make positive and negative slew-rates to be same(or how can match n and p)?schematic pic. if ur using 2 stage amp then output current mismatch b/w n and p will cause positive & neg. slew rate to be different....
Yeah we need to have enough phase margin,but why don't I get overshoots for rising output??overshoots normal as long as u have enough phase margin the overshoot will dampen out.
Yeah you are right,I need to switch OTA output between two DACS.Can I use simple 2:1 mux for this switching as this needs to Carry around 1mA currenti dont understand ur architecture. as i see it there is a buffer that drives into 2 DAC capcaitor blocks in a time interleaved fashion. is that what are u using or something different
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