Design two stage op-amp using gm/id

[livecf]

I try to design a two-stage amplifier using gm/id method. I calculated the gm for the input pmos pairs' gm using GBW, set the gm/id = 16 and using id/W chart to get the width of them. However, when I simulate it, the input pair gm is off by 30% (600u -> 400u).

Also, when I size the M5 using the current of M1 and M2, choose the gm/id = 10, and get the width using id/W. The same thing happened.

What might be the cause for this behavior?

Is it related to input common-mode voltage. I set the input common-mode to 0.5V and my VDD is 1.8V.

 

[arthorios]

Better to show the schematics from Virtuoso. Your transistors are probably out of saturation, you did not characterize (gm/id, id/W, etc.) them correctly, or you made a mistake in the design steps. gm/id will also change slightly with L, so it is better to characterize it for several lengths to increase the accuracy.
To maximize input and output voltage range/swings, common-mode voltages are usually set to about VDD/2.

 

[sutapanaki]

Did you put your amplifier in a feedback configuration to stabilize the DC operating point in your simulation?

 

[livecf]

Did you put your amplifier in a feedback configuration to stabilize the DC operating point in your simulation?

That would be a good idea. But could I get open loop dc gain and GBW from close loop configuration?

 

[arthorios]

That would be a good idea. But could I get open loop dc gain and GBW from close loop configuration?

If you are using Virtuoso, use iprobe (at the output of the OTA, inside the feedback loop) and run an STB analysis to get the loop gain. Under unity-gain configuration, loop gain frequency response is equal to the open-loop frequency response.

 

[sutapanaki]

That would be a good idea. But could I get open loop dc gain and GBW from close loop configuration?

arthorios explained it correctly. You can rely on proper biasing for open loop simulation of high gain amplifiers. You need a feedback at least for DC.​

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