Ravinder: From your plot I get a value id/(W/L)≈7µA for gm/id=10 , not 72µA.
No. For 45µA you'd get a W/L=45/7≈6.4 .With bias current as 45uA(considering slew-rate requirements and power dissipation) my W/L should be less than 1 and with this value of W/L i will never achieve a gain of 100.
Without more info about your circuit (schematic, op. voltage VDD) I can't help you further.@Erikl :but after setting W/L ratios how should I fix my input common mode voltage.
Only in strong inversion, not much in moderate and weak inversion, s. the 2 pages from David M. [Binkley]'s book "Tradeoffs and Optimization in Analog CMOS Design" (180nm process; separate plots for nmos & pmos). View attachment Binkley_gm_over_Id_for_diff_L.pdfDoes gm/id plot vary with channel length.
Depends on the process used and - by this - the usable op. voltage VDD. With VDD=5V a common input voltage range of 2V can easily be achieved. Neg. input voltages aren't possible on-chip anyway, they would have to be level-shifted or separated by SC method.In one paper I read it was shown that input swing as -1V to 1V. Will theren't be any linearity problems with such high swing
Depends on the process used and - by this - the usable op. voltage VDD. With VDD=5V a common input voltage range of 2V can easily be achieved. Neg. input voltages aren't possible on-chip anyway said:My question isn't how we manage negative voltages but will the gain linear because input voltage swing is very high
My question isn't how we manage negative voltages but will the gain linear because input voltage swing is very high
Input common voltage range means linear range!
I don't think so because as I think ICMR gives range of input voltage over which transistors are in active region and if the transistors are in active doesn't mean the gain would be same at every point in ICMR.Correct me if I'm wrong....
Do the gm/id plots vary with channel length?Because I'm getting different gm/id plots for 100n and 300n.Here is the plot I'm attaching gmid plot for L=300n,earlier I've attached gmid plot for 100n
I got GBW formula from text by Allen&Holberg.And at unity gain gain of th opamp must be 1 so Avnm9 may be equal to 12. how did u come to conclusion gm/Cc is the GBW. the 2 stage amplifier with miller cap. is a 2 pole system, the impedance that u see at the end of stage one will be miller cap will be multiplied by the gain of NM7 plus the output cap. so ur bw should be gm/(Cc*Avnm9 + cl)
yeah it is around 240u.do u get gm1 to be 225u in your sim (u can look at gm in result browser for the corresponding mos).
my channel lengths are 5 times minimum channel length.make the length of current mirrors atleast twice minimum length (if u plot i vs vgs/vds curves u will see the impedance difference).
try to match nm7 (width and length ) to nm0/nm1 this will improve matching and avoid unwanted vds mismatch and make the layout a lot lot easier.
yeah me too have same doubt whether to add overlap capacitance to Cc but even if add overlap capacitance(cgd) of both transistors(NM7 and PM10) to Cc it is coming out to be 245fF,yet my gm/(Cc+Cgd) is not close to what simulation value.ie u may have Cc+ Cgate(NM7) dont know how big this will be.
Sorry,I couldn't get youyou can isolate this by adding a zero volt DC source at the gate of NM7.
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