After doing full compilation of my design, i got the following warning messages. the documentation does not explain in detail on how to solve the problem. i do hope that somebody who had experienced this before could advice me.
Code:
Critical : Design Assistant Warning: Logic cell should not be used to generate inverted clock.
in Quartus docs, they said something about programmable invert but does explain in detail on how to use it. this is a problem of using inverter to provide oscillated signal.
Code:
Critical : Design Assistant Warning: Clock signal should not be a global signal.
why cannot?
Code:
Critical : Design Assistant Warning: Combinational logic used as reset signal should be synchronized.
i don't understand this message. every of my entity declaration and processes (in architecture) has their own asynchronous reset.
Code:
Warning: Design Assistant Warning: Design should not contain ripple clock structures.
again. inverted clock?
Code:
Warning: Design Assistant Warning: Clock signal source should drive only input clock ports.
how to define input clock ports?
Code:
Warning: Design Assistant Warning: External reset should be synchronized using two cascaded registers.
how to implement this?
some other questions. what is the technique usually used to reduce fan-out by coding (VHDL)? some of the components synthesized has fan-out more than its limit (50).
Critical : Design Assistant Warning: Logic cell should not be used to generate inverted clock.
in qu(at)rtus docs, they said something about programmable invert but does explain in detail on how to use it. this is a problem of using inverter to provide oscillated signal.
If you are trying to build an oscillator, the typical simulation oscillator won't work. A working oscillator requires analog (nondigital) components to set its base frequency. If there is a built-in oscillator, you can use that. It probably does not exist, in which case, you will need to use an external oscillator.