patinallin
Newbie level 3
Hi everyone!
I'm havind some troubles with Atmel CPLD and software Quartus II...
Okay, I do know I can't choose Atmel CPLD while compiling (cause the software was made by Altera for Altera devices). However, I've found a similar device to my Atmel 1508ASL CPLD: Altera EPM7128SLC84-15. Their pins are all the same, so are their configuration (vin, nummber of macrocells...)
All I need to do is getting and POF2JED converter (found in atmel website) in order to convert this file generated by the compiler... and program the Atmel using JED file!
It has worked here, for a small project (simple hexadecimal/decimal counter).
Now, I have been trying to use CPLD (Atmel 1508ASL) to build something bigger such as eeprom. I can get it simulated and it works fine, as expected. Then, I transfer the program to the device and guess what? Nothing works ):
Although it's a big project, the problem is not the dalays caused by that amount of logical gates. I am clocking it by myself (clock period is not shorter than 1 second!)
I am looking for an answer, why it is not working properly.
If any of you have an idea of what is going on, please let me know!
Thank you!
Regards,
Patrícia
I'm havind some troubles with Atmel CPLD and software Quartus II...
Okay, I do know I can't choose Atmel CPLD while compiling (cause the software was made by Altera for Altera devices). However, I've found a similar device to my Atmel 1508ASL CPLD: Altera EPM7128SLC84-15. Their pins are all the same, so are their configuration (vin, nummber of macrocells...)
All I need to do is getting and POF2JED converter (found in atmel website) in order to convert this file generated by the compiler... and program the Atmel using JED file!
It has worked here, for a small project (simple hexadecimal/decimal counter).
Now, I have been trying to use CPLD (Atmel 1508ASL) to build something bigger such as eeprom. I can get it simulated and it works fine, as expected. Then, I transfer the program to the device and guess what? Nothing works ):
Although it's a big project, the problem is not the dalays caused by that amount of logical gates. I am clocking it by myself (clock period is not shorter than 1 second!)
I am looking for an answer, why it is not working properly.
If any of you have an idea of what is going on, please let me know!
Thank you!
Regards,
Patrícia