Dear all,
I'm wondering why is the default value assign to a signal is always ignored? Is there any special constraints to assign a default value to a signal?
All I want to do is to assign a default value to a signal and use that value until external input supplies a new value, then the new value will be assigned to the signal for usage.
Help please, as I want to set a default value rather than using a reset pin to do those signal value initializations.
Thanks in advance!
If you synthesize a design default values are ignored due to the structure of CPLDs and FPGAs. The only way to implement default values is to set the value with a statement in a reset process.
architecture behavioural of test is
begin
process (reset, clk, next_value)
begin
if (reset = '1') then
value <= "0000";
elsif (clk'event and clk = '1') then
value <= next_value;
end if;
end process;
end behavioural;
Have a look to Quartus help on "Power-Up Level logic option"
This option can be set in the Assignment Editor (Assignments menu). This option is available for all Altera devices supported by the Quartus II software.