what is meant by dummy modules...
i have simulated the core testbench and it is working fine...
my problem is of not getting the simulation result due to the complexity in integarting my design with the core... have u tried the testbench...
i need to assign the data (which is output from other module) to the input pins of the core, i.e., data_real_in & data_imag_in. here i face the problem while assigning data to input pins of the core , i am unable to follow the control signals of the core...
pls help me... i am struck with my project at this point... without fft result i cant continue further... or do u know any link where i could find a fft function...i need 2K-point FFT, likely in verilog.
thank you