sensei616
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I just recently started learning VHDL and this particular error keeps coming up when trying to compile in quartus 2. I've been trying to figure out whats wrong but it looks like it should be correct. The program is supposed to be a divide by 2^x clock prescaler. It works by having a incrementing counter. And then based on how many divide by two stages needed tie the clock output to the proper counter bit.
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY ch4prescaler IS
PORT(
clock_in :IN STD_LOGIC;
pre_sel :IN std_logic_vector(3 downto 0);
clock_out :OUT STD_LOGIC);
END ch4prescaler ;
Architecture design OF ch4prescaler IS
signal count_value :unsigned(3 downto 0); <------Error points to this line
BEGIN
clock_out <= count_value(0) when pre_sel= 0 else
PROCESS(clock_in,pre_sel) is
BEGIN
if(rising_edge(clock_in)) then
count_value := count_value+1;
end if;
end process;
end architecture;
(Error (10482): VHDL error at Ch4Prescaler.vhd(13): object "unsigned" is used but not declared)
This is the error that is popping up, I've tried writing the code with count_value as a variable declared inside the process but that doesn't help. Anyone know what I'm doing wrong. Any help would be appreciated.
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY ch4prescaler IS
PORT(
clock_in :IN STD_LOGIC;
pre_sel :IN std_logic_vector(3 downto 0);
clock_out :OUT STD_LOGIC);
END ch4prescaler ;
Architecture design OF ch4prescaler IS
signal count_value :unsigned(3 downto 0); <------Error points to this line
BEGIN
clock_out <= count_value(0) when pre_sel= 0 else
count_value(1) when pre_sel= 1 else
count_value(2) when pre_sel= 2 else
count_value(3) when pre_sel= 3 else
count_value(4) when pre_sel= 4 else
count_value(5) when pre_sel= 5 else
count_value(6) when pre_sel= 6 else
count_value(7) when pre_sel= 7 else
count_value(8) when pre_sel= 8 else
count_value(9) when pre_sel= 9 else
count_value(10) when pre_sel= 10 else
count_value(11) when pre_sel= 11 else
count_value(12) when pre_sel= 12 else
count_value(13) when pre_sel= 13 else
'0';PROCESS(clock_in,pre_sel) is
BEGIN
if(rising_edge(clock_in)) then
count_value := count_value+1;
end if;
end process;
end architecture;
(Error (10482): VHDL error at Ch4Prescaler.vhd(13): object "unsigned" is used but not declared)
This is the error that is popping up, I've tried writing the code with count_value as a variable declared inside the process but that doesn't help. Anyone know what I'm doing wrong. Any help would be appreciated.
