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Quartis II and Verilog: Stealthily skipping code synthesis?

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IBNobody

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Here's a little feature with Quartus II that's giving me fits.

I'm trying to create a PLD project using Verilog in Quartus, but I have a bug in my code somewhere. Because of the bug, though, Quartus is deciding to optimize my design. A large portion of my design is no longer being synthesized.

How can I get Quartus to tell me when it's doing this sort of thing?

- Nobody
 

shark

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but i have not meet such an instance,maybe sometimes when it finds a simple way to build FPGA,it just operate in its usual way.
 

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