IBNobody
Junior Member level 1

Here's a little feature with Quartus II that's giving me fits.
I'm trying to create a PLD project using Verilog in Quartus, but I have a bug in my code somewhere. Because of the bug, though, Quartus is deciding to optimize my design. A large portion of my design is no longer being synthesized.
How can I get Quartus to tell me when it's doing this sort of thing?
- Nobody
I'm trying to create a PLD project using Verilog in Quartus, but I have a bug in my code somewhere. Because of the bug, though, Quartus is deciding to optimize my design. A large portion of my design is no longer being synthesized.
How can I get Quartus to tell me when it's doing this sort of thing?
- Nobody