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PXA270 and SDRAM routing problems

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Sep 16, 2004
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pxa270 sdram

Hi all,

I'm having troubles in routing the system bus of a PXA270 based board.

There are two low-power 32-bit wide SDRAM (MT48H16M32LFCM-75) and two 16-bit wide flash attached to the system bus. Furthermore each signal (address, data, control) of the system bus is then buffered and routed to a connector.

Therefore there are 4 to 5 loads connected to each signal.

The most critical device is the SDRAM chip. In fact, accordingly to the SDRAM and the PXA270 datasheet (, I have only 600ps of setup margin during SDRAM read operations, because the setup time required by the PXA270 is 3ns, the memory clock frequency is 104MHz and the access time of the SDRAM is 6ns (that is, I can theoretically achieve a maximum setup time of 3.6ns).

However, in the PXA270 design guide (, the memory controller layout guidelines are very confusing.

First of all, they suggest a balanced T topology for all the signals except SDCLK and SDCAS which shall be routed in a daisy-chain topology. Why such difference?

Furthermore, the design guide states: "The SDCLK driver signal quality is very important for read cycles. The recommendations helps maintain non-monotonic clock edge for the return clock with the help of Schmitt’s trigger of PXA27x SDCLK input path buffer". What does it means?
And what do they mean for "SDCLK input path buffer"? (which is mentioned neither in the developer manual, nor in the data sheet).

Moreover, the trace lengths seem to be extremely long: with the suggested trace lengths (5 to 6 inches for the clock), the typical delay is about 1ns, therefore the setup time during data reads would be (in the best case, neglecting the databus delay) smaller than 2.6ns, that is smaller than the PXA270 requirements (and I noticed that almost all the 1.8V, 133 MHz SDR SDRAM memories have an access time of about 6 ns).

Has anyone of you dealt with the PXA270?

Can you give me some recommendation/explanations? What was your topology?

And the maximum trace lengths?



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