Pulse extennsion in Fast to Slow clock crossing

[niraj_m]

Hi ,

Anyone help me to know the circuit for pulse extender for a signal which is crossing from fast clock to slow clock.

Thanks in Advance
Niraj

 

[AdvaRes]

Use a handshake protocol.

 

[niraj_m]

We would have used handshake mechanism if the signals generated is within the core of asynchronous interface . However here the 'cntrl' signal comes from standard APB bus wherein I have no option to ask the master interface to generate a hand shake signal . In such scenarios how do we extent the signal crossing faster clock to slower one .

 

[bulx]

Isnt there a way to tell this APB bus "hold on, Im not ready"? If not, how are you sure that you working on the slower clock wont miss some of the transaction requests coming from the faster bus?

one coarse way would be to use asynch flipflop to hold the request till your slower clock sees it and resets it, and hope you wont get requests faster than you can process. Neater would be to us a FIFO, this also that the rates match on the average.

-b