oberstet
Newbie level 6

Hi all,
I am designing a clock tree / distribution network for my device, which has various clocking needs, and requires a stable, phase synchronous clock tree throughout the whole system for the following frequencies:
* 30.72 MHz
* 25.0 MHz
* 24.0 MHz
For that, I've designed the clock tree like this:
1. Clock source: TCXO at 38.4 MHz with 0.5ppm over -40 to +85°C (using Epson TG2016SMN 38.4000M-MCGNNM0)
2. /5 x 4 == 30.72MHz => 1x single-ended 50R
3. /192 (/64/3) x 125 == 25.00 MHz => 2x single-ended 50R
4. /8 x 5 == 24.00 MHz => 3x single-ended 50R
For mere 1:1 buffering as well as proper forming of the clipped-sine-wave output of the TCXO into LVCMOS (at 3.3V) I have identified the following chip as suitable:
Renesas 5PB1216 (a 2.5 V to 3.3 V 1:6 TCXO / LVCMOS High-Performance Clock Buffer)
My questions:
a) Anything wrong "in principle / general" with my clock tree design?
b) What I am missing is a simple solution for the integer multiplications/divisions that retains the clock stability, phase synchronicity and low phase noise.
I would be grateful for any tips or hints, in general, and specifically rgd suitable chips! A simple and cost effective solution .. I definitely would like to avoid adding "complex" things like an FPGA if possible.
Thanks a lot and kind regards,
/Tobias
PS: I am actually a software engineer. And new to hardware. I am way out of my "normal" world, so please be gentle and forgiving with me. Your Karma will be happy, promise
I am designing a clock tree / distribution network for my device, which has various clocking needs, and requires a stable, phase synchronous clock tree throughout the whole system for the following frequencies:
* 30.72 MHz
* 25.0 MHz
* 24.0 MHz
For that, I've designed the clock tree like this:
1. Clock source: TCXO at 38.4 MHz with 0.5ppm over -40 to +85°C (using Epson TG2016SMN 38.4000M-MCGNNM0)
2. /5 x 4 == 30.72MHz => 1x single-ended 50R
3. /192 (/64/3) x 125 == 25.00 MHz => 2x single-ended 50R
4. /8 x 5 == 24.00 MHz => 3x single-ended 50R
For mere 1:1 buffering as well as proper forming of the clipped-sine-wave output of the TCXO into LVCMOS (at 3.3V) I have identified the following chip as suitable:
Renesas 5PB1216 (a 2.5 V to 3.3 V 1:6 TCXO / LVCMOS High-Performance Clock Buffer)
My questions:
a) Anything wrong "in principle / general" with my clock tree design?
b) What I am missing is a simple solution for the integer multiplications/divisions that retains the clock stability, phase synchronicity and low phase noise.
I would be grateful for any tips or hints, in general, and specifically rgd suitable chips! A simple and cost effective solution .. I definitely would like to avoid adding "complex" things like an FPGA if possible.
Thanks a lot and kind regards,
/Tobias
PS: I am actually a software engineer. And new to hardware. I am way out of my "normal" world, so please be gentle and forgiving with me. Your Karma will be happy, promise