PTM layout thickness

[MohsenS]

hi everybody,

I'm using PTM 90nm library and i want to understand thickness of different layers (silicon, metal and Sio2 layers).
can i understand this from library file? is there any other source?

 

[erikl]

From the model file(s) you can only get the SiO₂ gate layer thickness: toxp is the physical thickness=1.4nm .
The field oxide is a factor of 2..3 thicker.

The polysilicon thickness usually is 17..20% of the process size, i.e. 15..18nm for a 90nm process.

For the interconnect thicknesses (Al and/or Cu) I've found the following table:
There's an error in the authors indication, sorry, should mean: Etienne Sicard & Sonia Delmas Bendhia

The insulator thicknesses between the metal layers (SiO₂ or Si-oxynitride or low K material) are about a factor of 2..4 larger than the process size.