PSFB Peak and Valley Switching

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sabu31

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Dear All,

I am testing a PSFB controlled using UCC28950.

I want to know whether the delay between the Top and Bottom Switches of same leg are correct . I am attaching the waveforms
 

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  • Drain_Source_voltage.pdf
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~600 ns dead time must always be > FET turn off time when hot

so lots of margin at room temp I think.

Clean up your trace noise with proper probing, and very short gnds
PWM below
 
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I am getting a spike in input current. Is this correct or there is some timing mismatch in delays. Also what is cause for the notches in the transformer voltages. The schematic is attached showing current measurement point and the devices chosen for measurement.
 

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  • SCHEMATIC_LAYOUT_PSFB.pdf
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  • Waveform_.png
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I am attaching my Primary Side device and QA and Secondary Device QF (synchronous) gating signals. Should The QF be on more than QA or is this sufficiently
 

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  • tek00085_GateWaveforms_Prototype.png
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Both as long as F-A is always greater than zero at max junction temp to avoid shoot-thru since delays/risetime increase with T.
So there must be safety margin and that means a RD snubber may be needed if you want to clamp V=LdI/dt, yet only at 100% PWM, since this is a tri-level driver. ( or ought to be)
 

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There is deadtime ( ~ 100nS ) and there is way too long deadtime 2uS

long is good for IGBT's, but 100nS - 250nS is for fast mosfets
 

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