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PSFB cycle-by-cycle current limiting

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Porsche

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Hello,

I am designing a CMC PSFB converter based on UCC3895. I ran into a problem with cycle-by-cycle current limiting.

When the voltage at the CS pin reaches the 2V threshold, the duty cycle starts to change rapidly and asymmetrically. This causes audible noise and could even lead to primary TX saturation (in this case 2.5V threshold kicks in, restarting the IC).

I expect that the duty cycle should change smoothly and symmetrically, reducing the output voltage when the load resistance decreases, thus limiting the output current. But that occurs only when the load resistance is too low, when duty cycle is already around 55% and less. From ~55% down to ~0% duty cycle changes smoothly and symmetrically. From ~80% down to ~55% duty cycle changes rapidly and asymmetrically.

Here's what I've tried so far:
  1. to remove oscilloscope probe from the summing point;
  2. to add more/less slope compensation;
  3. to add more/less filtering to the current signal;
  4. to add DC offset (~1V) to the summing point;
  5. to add/remove DC-blocking capacitor in series with main TX.
Any ideas on how to fix this?

Input voltage 350V, Output voltage 50V, Npri/Nsec=5, Ncs=100, current slope compensation ~0.19V/us, inductor down slope current transferred to the voltage is ~0.18V/us. Voltage control loop seems to work fine under all conditions. Stable 50V at the output without rapid duty cycle variations.

Yellow signal - voltage at the summing point (just compensating ramp), no input (350V) voltage applied.
scope_5.png


Yellow signal - voltage at the summing point. Blue signal - output diode voltage. Red signal - output current. Converter runs, 50V and 6 Ohm load at the output.
scope_0.png


Yellow signal - voltage at the R18 (40 Ohm). Blue signal - output diode voltage. Converter runs, 50V and 6 Ohm load at the output.
scope_4.png


Yellow signal - voltage at the summing point. Blue signal - output diode voltage. Red signal - output current. Converter runs, 50 V at the output and current protection just about to trip.
scope_1.png


Yellow signal - voltage at the summing point. Blue signal - output diode voltage. Red signal - output current. Converter runs, ~50 V at the output and current protection is tripping. Audible noise appears, you can see duty cycle variations on a blue waveform.
scope_2.png
scope_3.png
 

Attachments

  • Schematic_PSVBV1_2023-03-10.png
    Schematic_PSVBV1_2023-03-10.png
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  • block.PNG
    block.PNG
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Solution
Hi guys! I am glad to tell you that I've found the issue.
The main reason for such oscillatory behaviour was lack of slope compensation. The reason I didn't notice this from the beginning is that when the load current was low, the compensation ramp was sufficient, and when the load current was increased (and of course voltage on CT also increased), the compensation ramp just drowned in the ramp from the current sensor. From what I understand this effect was caused by the relatively high output impedance of Q5 (BC337-40) due to the high value of R26(16k). Changing the R26 resistor to a lower resistance resistor <1k completely solved the oscillation problem.
The second problem with unipolar CT (TCS2.1) (asymmetric green waveform) was...
If you operate right banged up to the duty cycle limit, or the current sense threshold limit, then you will get noisy operation. Also, you dont want the series cap in the primary bridge as you are in CMC.
Attached please find a PSFB sim in LTspice......you can change it so its like yours, get it working there, then carry back across to the UCC3895.
It is good to see you post the full schem.....PSFB is a standard topology so you are not giving away any IP.
Also, to generally get less noise in any converter, increasing the gate series resistance helps...though not too much ...in PSFB at full load you should be getting ZVS so low gate series resistance not needed.....use diode turn off, to make the OFF going much faster.

As you know, in PSFB, the "leakage" inductance robs you of duty cycle especially at heavy load.......thats the main reason why your duty cycle increases when above 50% load.....below that, and at light load, the inductor current eventually goes DCM so duty cycle will get very small at light load.
 

Attachments

  • PSFB_2kW.zip
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Last edited:

Thanks for your sim, I will try to repeat this process in LTspice. Please note that the schematic is attached to my first post in the "Attachments" section.

Shorting the DC blocking capacitor makes no difference, I left it there just to be safe.
As you know, in PSFB, the "leakage" inductance robs you of duty cycle especially at heavy load.......thats the main reason why your duty cycle increases when above 50% load.....below that, and at light load, the inductor current eventually goes DCM so duty cycle will get very small at light load.
Yes, but in my setup the minimum load (6 ohm resistor) provides the CCM.

The main problem is "noisy" operation near the current sense threshold limit. After the current limit is reached I have to add about 5-10A more, so that the sudden variations of the duty cycle stop. Therefore, there is quite a wide noise range between the moment when the protection is just triggered and when the output voltage under the action of this protection decreases smoothly and evenly.
 

The main problem is "noisy" operation near the current sense threshold limit.
yes thats very often the case with CMC...can you back off the limit a bit? (ie reduce the value of your sense resistor.)
 

Yes, I tried different CS resistor values of 20-70 ohms, but that "noisy" band is still pretty wide in all cases. How can this effect be reduced? Or is this a common problem with CMC, then more precise current limitation needs to be done with a separate circuit? What is the usual solution here?
 

Most suspect thing in your waveforms is that the shape/slope of the waveform at the summing point is changing each cycle. Subharmonic oscillation can cause the pulse width to change cycle to cycle, but it should not cause the slope of the current sense signal to change. Looks like some magnetic component is saturating somewhere.

Do you have a high frequency current probe you can use to measure the transformer primary current waveform, or the current in L1?
 

Unfortunately, my current probe only has a bandwidth of 100 kHz so I can't measure primary current directly. The most accurate measurements I have are those obtained with a current transformer.
Here is the voltage across R18 (current transformer load resistor) at the moment when the current protection just begins to trip. I don't see much difference in the slope here, but it is clearly visible that with each cycle the average current rises gradually reaching threshold and then falls again and everything repeats. This process has a stepped nature. (Yellow signal here will actually be divided by about 2 when summing with compensation ramp, so it is more correct to say here that the sum reaches the 2V threshold)
Yellow signal - voltage at the R18 (40 Ohm). Blue and red signals are voltages at the output diodes.
scope_9.png
scope_10.png

Asymmetry in the duty cycle caused by this phenomenon probably leads to transformer saturation...

P.S. Without current protection, the converter operates stably even with a large load, about 2 kW. All problems start when the current protection kicks in. And this is true even at low load, e.g. if the current protection is set to 700 W.
 
Last edited:

Things to consider:
1. Your current transformer is on the TX primary, but because of the clamping diodes D9+D10 this isn't equal to the current in L1 and the FETs on that side of the bridge. It's plausible that L1 is saturating, even if the TX is not.
2. Your current sense transformer may also be saturating (I don't see evidence of this in the waveforms, but it might not be obvious...)
3. In the vast majority of PSFB designs I've seen, current sensing is not done on the bridge outputs (either on the TX or L1), often on the high side of the bus using a current transformer with a simple half-wave-rectified secondary (meaning it requires a reset every cycle).

It's been a while since I looked closely at PSFB designs, but I'm betting your problem is related to your current sensing. Either the choice of where current is sensed, or an issue in the sense circuit itself. I strongly recommend you get a reliable DC-coupled current sensor to compare against.
 

Hello,

I am designing a CMC PSFB converter based on UCC3895. I ran into a problem with cycle-by-cycle current limiting.

When the voltage at the CS pin reaches the 2V threshold, the duty cycle starts to change rapidly and asymmetrically. This causes audible noise and could even lead to primary TX saturation (in this case 2.5V threshold kicks in, restarting the IC).

I expect that the duty cycle should change smoothly and symmetrically, reducing the output voltage when the load resistance decreases, thus limiting the output current. But that occurs only when the load resistance is too low, when duty cycle is already around 55% and less. From ~55% down to ~0% duty cycle changes smoothly and symmetrically. From ~80% down to ~55% duty cycle changes rapidly and asymmetrically.

Here's what I've tried so far:
  1. to remove oscilloscope probe from the summing point;
  2. to add more/less slope compensation;
  3. to add more/less filtering to the current signal;
  4. to add DC offset (~1V) to the summing point;
  5. to add/remove DC-blocking capacitor in series with main TX.
Any ideas on how to fix this?

Input voltage 350V, Output voltage 50V, Npri/Nsec=5, Ncs=100, current slope compensation ~0.19V/us, inductor down slope current transferred to the voltage is ~0.18V/us. Voltage control loop seems to work fine under all conditions. Stable 50V at the output without rapid duty cycle variations.

Yellow signal - voltage at the summing point (just compensating ramp), no input (350V) voltage applied.
View attachment 181689

Yellow signal - voltage at the summing point. Blue signal - output diode voltage. Red signal - output current. Converter runs, 50V and 6 Ohm load at the output.
View attachment 181692

Yellow signal - voltage at the R18 (40 Ohm). Blue signal - output diode voltage. Converter runs, 50V and 6 Ohm load at the output.
View attachment 181690

Yellow signal - voltage at the summing point. Blue signal - output diode voltage. Red signal - output current. Converter runs, 50 V at the output and current protection just about to trip.
View attachment 181694

Yellow signal - voltage at the summing point. Blue signal - output diode voltage. Red signal - output current. Converter runs, ~50 V at the output and current protection is tripping. Audible noise appears, you can see duty cycle variations on a blue waveform.
View attachment 181696View attachment 181697
1) You should remove the decoupling cap since your cct operates in current mode control. Also the decoupling cap reduces the cct's dynamic response since it collects dc offset voltage. For example, when duty cycle is changing quickly from low to high, the dc offset voltage will be added to one side of output voltage polarity and be subtracted the other side of the output votage.
2) After decoupling cap removal, you need to put the air gap in the main transformer to make saturating current smoother. Since you already remove the decoupling cap, your main transformer will run to saturation on one side of the voltage polarity but once the current transformer detects that saturating peak current, that side of votage is turned off suddenly due to cycle-by0cycle current limiting feature but the duty cycle on the other side is still ok, making the transformer flux become balance again.
 

Thanks for the tips. I tried a unipolar transformer TCS2.1, 2.2, but the waveform from it is no good at all. For some reason the signal there has a reverse slope in every second cycle (QC, QB conducting). Please note the new schematic, with the colored numbers I have marked the measurement points of the signals.
Sheet_1 copy copy.png

round cst.png

(I tried with different types and core sizes of TCS2 - same result )
I found that it has to do with the resonant choke L1. If you short the resonant choke L1, the signal is equalized. I can not understand what could be the reason (diode reverse recovery maybe?). The diodes D9,D10 are definitely OK. I tried both IDW30G65C5 and IXYS DSEI30-10A.

Here is waveforms when L1 shorted
round cst lshort.png

For this reason I decided to continue with the bipolar current sensor, where the signal is symmetrical and does not depend on L1. At least until the current protection trips.
Here is another interesting measurement. You can see that during the triggering of the current protection the transistor QD is closed more than 50% of the cycle time. I understand that this is necessary for phase shifting, but it definitely causes voltage asymmetry on the main transformer.
d closed more50.png
d closed more50 2.png


I strongly recommend you get a reliable DC-coupled current sensor to compare against.
Yes, I could really use it in the future. Do you have any recommendations? What do you use? I think the Micsig CP2100B might be a good choice, what do you think?
--- Updated ---

1) You should remove the decoupling cap since your cct operates in current mode control. Also the decoupling cap reduces the cct's dynamic response since it collects dc offset voltage. For example, when duty cycle is changing quickly from low to high, the dc offset voltage will be added to one side of output voltage polarity and be subtracted the other side of the output votage.
2) After decoupling cap removal, you need to put the air gap in the main transformer to make saturating current smoother. Since you already remove the decoupling cap, your main transformer will run to saturation on one side of the voltage polarity but once the current transformer detects that saturating peak current, that side of votage is turned off suddenly due to cycle-by0cycle current limiting feature but the duty cycle on the other side is still ok, making the transformer flux become balance again.
Hi, thanks for your recommendations. I actually already tried to do exactly everything you described.
1) decoupling cap - shorted.
2) air gap in the main transformer - added.
And then everything works as you described here. And the saturation of the transformer becomes softer (the 2.5V current protection threshold is no longer reached). Everything works properly, except for the oscillations of the duty cycle when entering the cycle-by-cycle current limit (long pulse, long pulse, short pulse - repeat...). These oscillations are on as soon as the protection threshold is reached and continue until I increase the current by so much that the duty cycle is no longer about 50%. Then when I increase the current even more everything works perfectly stable.
 
Last edited:

The problem with your unipolar current sense transformer is that, because of your very high duty cycle, it would require very high peak voltages to properly reset each cycle. Your clamping diodes there are probably preventing it from functioning properly. Honestly, for operation at such high duty cycle (like >75%) I wouldn't bother using a current sense transformer. Could you try adjusting the turns ratio on your isolation transformer so that you don't require such high duty cycles? That might make everything easier.

Interesting that removing L1 results in the issue going away, but that's likely going to hurt your power efficiency. I can't be certain why removing L1 helps, but consider that L1 effectively reduces the voltage applied to the primary, and thus your duty cycle must increase as L1 increases. So perhaps removing L1 caused the duty cycle to drop a bit, and that's actually the reason the behavior changed.
 
Thanks for the tips. I tried a unipolar transformer TCS2.1, 2.2, but the waveform from it is no good at all. For some reason the signal there has a reverse slope in every second cycle (QC, QB conducting). Please note the new schematic, with the colored numbers I have marked the measurement points of the signals.
View attachment 181761
View attachment 181762
(I tried with different types and core sizes of TCS2 - same result )
I found that it has to do with the resonant choke L1. If you short the resonant choke L1, the signal is equalized. I can not understand what could be the reason (diode reverse recovery maybe?). The diodes D9,D10 are definitely OK. I tried both IDW30G65C5 and IXYS DSEI30-10A.

Here is waveforms when L1 shorted
View attachment 181763
For this reason I decided to continue with the bipolar current sensor, where the signal is symmetrical and does not depend on L1. At least until the current protection trips.
Here is another interesting measurement. You can see that during the triggering of the current protection the transistor QD is closed more than 50% of the cycle time. I understand that this is necessary for phase shifting, but it definitely causes voltage asymmetry on the main transformer.
View attachment 181764View attachment 181765


Yes, I could really use it in the future. Do you have any recommendations? What do you use? I think the Micsig CP2100B might be a good choice, what do you think?
--- Updated ---


Hi, thanks for your recommendations. I actually already tried to do exactly everything you described.
1) decoupling cap - shorted.
2) air gap in the main transformer - added.
And then everything works as you described here. And the saturation of the transformer becomes softer (the 2.5V current protection threshold is no longer reached). Everything works properly, except for the oscillations of the duty cycle when entering the cycle-by-cycle current limit (long pulse, long pulse, short pulse - repeat...). These oscillations are on as soon as the protection threshold is reached and continue until I increase the current by so much that the duty cycle is no longer about 50%. Then when I increase the current even more everything works perfectly stable.
Since your circuit is so complicated, I suggest you simplify it first. If I were you, I will generate the EAOUT pin to be an adjustable smooth dc voltage, using voltage follower circuit and then try to adjust the EAOUT voltage from low to high and then diagnose those related pins. If everything looks ok, closing the voltage loop.
 

Since your circuit is so complicated, I suggest you simplify it first. If I were you, I will generate the EAOUT pin to be an adjustable smooth dc voltage, using voltage follower circuit and then try to adjust the EAOUT voltage from low to high and then diagnose those related pins. If everything looks ok, closing the voltage loop.
Seconding this. I believe the issue is in the peak current mode control loop, and debugging it would be easier if you eliminated the voltage control loop. Or, alternatively, reduce the voltage control bandwidth greatly so that its gain is nearly zero over short timespane.
 

With such a small Lout you need a lot of slope comp above 45% of a full pulse

your slope comp adding ckt is not the best

the CT would be better placed in series with the Tx

For where the CT is, full wave rect of the CT is causing issues - as it cannot get high enough reset volts for higher PWM on times - you should have a single 100V diode and the resistor ( noting dot notation ) - this is the root cause of your issues.

Finally you cannot have a blocking cap AND peak curr mode control - this does not work for obvious reasons.

It is either one or the other.
 

the CT would be better placed in series with the Tx

For where the CT is, full wave rect of the CT is causing issues - as it cannot get high enough reset volts for higher PWM on times - you should have a single 100V diode and the resistor ( noting dot notation ) - this is the root cause of your issues.
In principle I can't see anything wrong sensing current directly on the TX primary, but I can't find any specific implementations of this when I search around. Seems all the app notes from manufacturers are recommending sensing current outside the bridge, mostly on VBUS.

If using a current sense transformer on the TX primary, I don't see how one could design a circuit which would discriminate the voltage from a reset pulse and an actual sensed current in the opposite direction.
Finally you cannot have a blocking cap AND peak curr mode control - this does not work for obvious reasons.

It is either one or the other.
The OP mentioned early on that removing the blocking cap didn't affect this behavior, but I agree that it should never be used in a peak CMC circuit.
 

1679255399774.png


Above shows the correct method if the CT is on the supply line ( pos or neg ) - not shown is the small amount of bus cap needed across the fets after the CT for turn off protection of the fets

R reset is not needed due to the capacitance of the wdg on the CT - the diode should be a very fast type and at least 75V

When the CT is placed in series with the TX - a normal full bridge of schottky diodes provides the rectified current into the burden resistor - this provides accurate current information - regardless of the lack of understanding of the poster above.
--- Updated ---

1649235552995-png.175288


A CT in series with the primary will faithfully reproduce the pri curr as shown above - a simple burden resistor only, will give an exact but bipolar output ( as above ) - FWR with schottkies will give the FWR version - suitable for feeding a control IC

( the same logic applies as to why a 500:1 CT on the mains does not need a reset circuit )
 
Last edited:

    mtwieg

    Points: 2
    Helpful Answer Positive Rating
Hi guys! I am glad to tell you that I've found the issue.
The main reason for such oscillatory behaviour was lack of slope compensation. The reason I didn't notice this from the beginning is that when the load current was low, the compensation ramp was sufficient, and when the load current was increased (and of course voltage on CT also increased), the compensation ramp just drowned in the ramp from the current sensor. From what I understand this effect was caused by the relatively high output impedance of Q5 (BC337-40) due to the high value of R26(16k). Changing the R26 resistor to a lower resistance resistor <1k completely solved the oscillation problem.
The second problem with unipolar CT (TCS2.1) (asymmetric green waveform) was caused by misconnection of the cathode pin of D9. It was connected to the + of C1 directly in other words it was connected before the current sensor. As soon as I connected it according to the schematic the appropriate waveform was obtained.
I think I will respin PCB according to the obtained knowledge. Not sure yet which CT I will use in the final design. TI recommend using a unipolar solution, but bipolar works as well, it is more accurate and it does not need to be reset.

All in all I want to thank every one of you for your help and ideas! Thank you guys!
your slope comp adding ckt is not the best
What is the most common signal adding scheme?
 

    mtwieg

    Points: 2
    Helpful Answer Positive Rating
Solution
View attachment 181819

Above shows the correct method if the CT is on the supply line ( pos or neg ) - not shown is the small amount of bus cap needed across the fets after the CT for turn off protection of the fets
Right, this is basically what I've seen in 90% of app notes (for offline converters, anyways). My assumption is that this is preferred mainly because CMRR is not a concern, compared to sensing on the primary. The poorer bus decoupling is not a great tradeoff though IMO...
When the CT is placed in series with the TX - a normal full bridge of schottky diodes provides the rectified current into the burden resistor - this provides accurate current information - regardless of the lack of understanding of the poster above.
--- Updated ---

1649235552995-png.175288


A CT in series with the primary will faithfully reproduce the pri curr as shown above - a simple burden resistor only, will give an exact but bipolar output ( as above ) - FWR with schottkies will give the FWR version - suitable for feeding a control IC
Ok so here you're saying that a FWR+burden resistor on a primary current sensor is fine. But previously you said:
For where the CT is, full wave rect of the CT is causing issues - as it cannot get high enough reset volts for higher PWM on times - you should have a single 100V diode and the resistor ( noting dot notation ) - this is the root cause of your issues.
Maybe in that post you were referring to the bus current sent transformer he added (TCS2), not the original one (TCS1)?
--- Updated ---

From what I understand this effect was caused by the relatively high output impedance of Q5 (BC337-40) due to the high value of R26(16k). Changing the R26 resistor to a lower resistance resistor <1k completely solved the oscillation problem.
I suppose this makes sense. But IMO it's not really a matter of Q5's output impedance being too high (a small signal thing), but rather of Q5's bias (a large signal thing). In some of your waveforms, node 1 (the summing point) climbs to over 2.1V. R26/R27 divide that down to a thevenin equivalent of ~1.95V. Meanwhile, the ramp on the CT pin will only go up to 2.5V (the threshold of the CT pin). This means that there won't always be enough voltage to forward bias Q5's base-emitter. Maybe this explains why the slope of your node 1 waveforms suddenly increases when >2V.

By reducing R26, the thevenin voltage at Q5's emitter is reduced, allowing it to maintain forward bias. Lowering R26 to below 1K sounds excessive though.
1679316456938.png

The second problem with unipolar CT (TCS2.1) (asymmetric green waveform) was caused by misconnection of the cathode pin of D9. It was connected to the + of C1 directly in other words it was connected before the current sensor. As soon as I connected it according to the schematic the appropriate waveform was obtained.
Ah that makes sense, easy mistake to make. But I would still double check that D14 isn't preventing proper resetting of TCS2. Also should still remove C29.
What is the most common signal adding scheme?
For these "unitrode" style PWM controllers, basically what you're doing. But it's also recommended to put a DC blocking cap between the ramp circuitry and the current sense signal. This at least prevents their DC biasing from interacting with each other.

Keep in mind that these changes are probably going to have secondary effects, like changing the gain of the CMC loop, or changing the peak current limit. You will likely have to adjust other components (R18, R12, R27, etc) as well.

The best thing about these kind of PWM controllers is that their internals are usually described very clearly by the datasheet, meaning you can build very good SPICE models (just don't ask TI for one, they'll tell you to use TINA, or spit in your face). I highly recommend making such a model so you can check for these sort of subtle issues easily.
 
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The best - if not the most common - method for a slope comp ramp is to derive it from the gate drive outputs via diodes and an RC ckt and a reset pulse to discharge the C

taking it off the timing cap almost always leads to tears at high power - and it introduces an offset.
--- Updated ---

Good work finding the D9 error - visual inspection finds > 90% of all errors
--- Updated ---

For some reason I thought your CT was in the positive supply - I see that it isn't - where it is will work just fine as long as the CT is away from magnetic interference from the TX or other magnetic and the CT is rated properly.

A CT in the supply line limits the max D to ~ 90% to allow for reset time.
 
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The ckt shown above for slope comp introduces a signal that is symmetrical about 0v, this can be an issue pulling the curr sense line below gnd at lower currents ...
 

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