Propagation Delay of Schematic VS Post-layout Simulation

[isaacnewton]

propagation delay between schematic layout

Dear All,

I am designing a 4-bit ALU (Full Custom Design) using Cadence. I did schematic simulation and post-layout simulation. I found the propagation delay for the schematic simulation is even greater than that for post-layout simulation. The delay for schematic simulation is about 1.5 ns, for post-layout simulation, it's about 1.3 ns.

Why this happens?

I think all my procedure is correct. Extraced (layout) circuit includes parasitic capacitance.

Did anybody meet the same problem? Thank you.

 

[khorram]

You mean that a 4-bit ALU has been designed in transistor level (full custom design) and you generate a custom layout manually without using standard cells. If so, you probably have some mistakes to generate layout and the L and W sizes are not equal in schematic & layout.
If you use standard cells, i think so, don't forget to extract SDF (standard delay format) for the cells and simulate the design extracted from layout based on it.

Regards,
KH

 

[isaacnewton]

If so, you probably have some mistakes to generate layout and the L and W sizes are not equal in schematic & layout.
If you use standard cells, i think so, don't forget to extract SDF (standard delay format) for the cells and simulate the design extracted from layout based on it.

I layout the circuit by myself. The layout passed LVS test, that means the Layout and the Schematic are the same, the Transistors sizes are the same.

Generally, considering Propagation Delay, how much difference the Schematic and Layout will be?

 

[isaacnewton]

Generally, the post-layout simulation delay should be greater than schematic simulation delay, right? Thank you.

 

[haosg]

it is realy curious, I guess you should run post-simulaiton with spice netlist.
the parasitics should make delay more than transistor.
If the condition for parasitics extraction is not correct?