Programming by JTAG OK <-> PROM serial programming KO

[System.out]

Hello,

Following the schematic below, i have a serial PROM with i can program successfully with iMPACT and a Xilinx S3-400 that i can also program successfully.

The problem is that when i remove the JTAG, and i want to program the FPGA from the serial PROM, INIT_B does not go low, why is it? I can not program the FPGA from the PROM.

I have been thinking on adding a 47K pull-down resistor on the INIT_B line, what do you think? Would that solve my problem?

 

[banjo]

FYI,

I do not believe that INIT needs a pull-down. You can externally hold INIT low to delay the startup of the FPGA. Otherwise, the FPGA internally holds INIT low until it completes its internal reset sequence. Then the FPGA releases INIT to allow startup to continue.
My guess is that your problem is your bit file. To program the FPGA via the JTAG port, you must configure your bitfile to use the JTAG clock. However, when programming from the PROM, the bit file must be configured to use the CCLK. Therefore, you need two separate versions of the bit file. One for the PROM and another for the FPGA directly through JTAG.

Your MODE pins seem to be set correctly. I would program the PROM, then remove the JTAG cable and power cycle the system. Monitor the CCLK, if the FPGA is properly being reset, you should see CCLK toggling. If CCLK toggles, but DONE never goes HIGH, then the wrong bit file is loaded into the PROM or there is a wiring problem between the PROM and the FPGA.