Programmable frequency divider from 1 to 32 division factor

[gilbertomaldito]

Does anybody know a circuit architecture for a programmable frequency divider that can divide from 1 to 32? I need it to divide by 1, 2, 3, 4, 5 upto 32 depending on its 4bit control signal.
please help

thanks

--andrew

 

[erikl]

Re: Programmable frequency divider from 1 to 32 division fac

You'd need 5bit to do that. Don't reinvent the wheel: Start with the standard circuit of a dedicated programmable divider/counter, e.g. MC14526 and its cascade application. You'll need 1 M/S-FF per bit, and about 5 more gates/bit.

 

[gilbertomaldito]

Hi Erikl

Yeah of course i need 5 bit (2^5=32) -> my mistake. Anyway do you have the circuit for it?

 

[erikl]

Re: Programmable frequency divider from 1 to 32 division fac

Anyway do you have the circuit for it?

Hi Andrew,
I already told you: MC14526 . You can download the dataSheet from here. See pp. 8 & 9 ;-)
Rgds, erikl

 

[gilbertomaldito]

Hi Erikl, thank you for your response. I looked at datasheet you told me. However, I cant figure out what circuit was used for the D-flipflop with the "T" pin. Do you know what the "T" pin in the DFF is for?

thank you again
--gilbert

 

[erikl]

Re: Programmable frequency divider from 1 to 32 division fac

Do you know what the "T" pin in the DFF is for?

Hi Andrew,
it's a Toggle-FF. For an explanation of the "T"-pin, s. this link , scroll down and search for "T flip-flops". Be aware that both the "C" and the "T" inputs in the 14526 dataSheet are negated.

Rgds, Erik
__
PS: Sorry, the YaBBC presentation of the URL link doesn't always work ;-)

 

[gilbertomaldito]

Hi erikl

If its a T flipflop, what about the "D" input? Is it a combination of a D and T flipflop?

Also, what do you mean when you say the C and T are negated? I cant see how they are negated in the circuit.

thanks for the response

--gilbert andrew

 

[FvM]

Re: Programmable frequency divider from 1 to 32 division fac

Is it a combination of a D and T flipflop?

You have to look at the circuit function to understand the meaning of the D and T inputs. It's actually a T Flip-Flop with an asynchronous preset.
The usage of "D" for the preset data is somewhat misleading.

what do you mean when you say the C and T are negated

As a fact, they are negated (negedge respectively active low) at the FF block. Find out what it means for the overall function.

 

[gilbertomaldito]

Hi FvM,

thanks for the response.
Do you happen to have the transmission gate circuit for the T-flipflop with asynchronous preset as you have described? or atleast the logic gates circuit?
I need to include it in my IC. I tried to search for the circuit of the Tff with preset, however, i really cant find it so far.

--gilbert andrew

 

[mawais]

Re: Programmable frequency divider from 1 to 32 division fac

Hi andrew!
I dont know how far you are with your current design, but I had some helping material that I thaught to share with you so that you have more ideas to do with.
The attached file shows how you can make a exactly an odd numberd divisible clock frequency generator. On the other hand we can easily divide a clock frequency by the powers of 2 (2,4,8,16,32.....)
So cascading different division circuits with different combinations of division factors you can divide your input frequency by any integral number.
Hope it will help you.
best regards,
Muhammad Awais.

 

[FvM]

I don't have a circuit. But TI CD4018 involves a similar D-FF with asynchronous preset, that can be modified to a T-FF, I think.
A transmission gate circuit is in the datasheet.

 

[erikl]

Re: Programmable frequency divider from 1 to 32 division fac

Do you happen to have the transmission gate circuit for the T-flipflop with asynchronous preset as you have described? or at least the logic gates circuit?

Hi Andrew,
below pls. find a schematic which converts a JK-FF into such T-FFs which are used in the 14526 dataSheet.

 

[gilbertomaldito]

Erikl, mawais and FVM, thank you very much for the help. It worked already. However, my problem now is how would I able to make its duty cycle 50%. I cant just pass it through a divide by 2 circuit to make it 50% because I really need to have a divide by N output.

Does anybody have an idea how to solve this problem?

 

[yego]

Re: Programmable frequency divider from 1 to 32 division fac

You could multiply your input signal by 2 before dividing it, and divide your divided signal by two on the output stage.
This way you should get 50% duty.

 

[erikl]

Re: Programmable frequency divider from 1 to 32 division fac

You could multiply your input signal by 2 before dividing it ...

I think it's better and easier to multiply the output signal by 2 : feed your divider output through a D-FF clock-controlled by the divider input signal, by this you should get the output delayed by one cycle of the input signal. Then you exor both signals (divider_output exor delayed_divider_output) and you attain a double frequency signal which can be divided by 2 for a 50% duty cycle.

Oh, sorry: This wouldn't work for a division ratio of 1 ;-)

 

[gilbertomaldito]

Re: Programmable frequency divider from 1 to 32 division fac

You could multiply your input signal by 2 before dividing it ...

I think it's better and easier to multiply the output signal by 2 : feed your divider output through a D-FF clock-controlled by the divider input signal, by this you should get the output delayed by one cycle of the input signal. Then you exor both signals (divider_output exor delayed_divider_output) and you attain a double frequency signal which can be divided by 2 for a 50% duty cycle.

Oh, sorry: This wouldn't work for a division ratio of 1 ;-)

Hi Erikl,

I dit what you told me, however, I still cant get the correct output with 50% duty cycle. Attached are my waveforms.

--andrew

 

[erikl]

Re: Programmable frequency divider from 1 to 32 division fac

I dit what you told me, however, I still cant get the correct output with 50% duty cycle.

Hi Andrew,
you're right, this doesn't work; it was my mind mistake, sorry! In this case I think the only chance is to follow yego's suggestion (above) : multiply the input frequency by 2 , then run this double frequency through your programmable divider and divide its output by 2.
Doubling the input frequency, however, is not so easy, if you don't have a higher frequency to generate the necessary delay (s.a. **broken link removed**). In such case you need to generate the delay by a - in IC design not so elegant - yet still working - method: either with RC-delay + Schmitt-Trigger, or - much easier - using the added gate delays of an inverter chain. This should work.
Rgds, erikl

 

[gilbertomaldito]

Hi Erik and yego,

Yeah, it worked. However, Im not confident with the delay especially becuase it may be varying through PVT. But anyway, thanks a lot. It worked already.

--andrew

 

[erikl]

Re: Programmable frequency divider from 1 to 32 division fac

Im not confident with the delay especially becuase it may be varying through PVT.

Of course you must make sure by postLayout simulation, that you have enough min. delay for ffP, max.V, min.T, and - for your max. input frequency - not too much delay for ssP, min.V & max.T cond.